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Embedded Wafer-Level-Packages: Fan-out WLP / Chip Embedding in Substrate - 2010 Report Product Image

Embedded Wafer-Level-Packages: Fan-out WLP / Chip Embedding in Substrate - 2010 Report

  • ID: 1257396
  • July 2010
  • Region: Global
  • 256 Pages
  • Yole Développement

FEATURED COMPANIES

  • 3D-Plus
  • Casio Micronics
  • Flip-chip International
  • LG Electronics
  • Panasonic
  • STMicroelectronics
  • MORE

Be ready for the next generation of IC packaging & substrate assembly waves!

MARKET TRENDS

Historically, embedded IC package technology is not new at all: several players such as Freescale with its RCP, Infineon with its eWLB and Ibiden for die embedding into PCB laminated substrates have developed dedicated technologies and process IP in this area for years. Benefits of embedded package integration include miniaturization, improvement of electrical and thermal performance, cost reduction and simplification of logistic for OEMs.
Things are moving really fast at the moment as this year, we see both Fan-out wafer level packaging and chip embedding into PCB laminate infrastructures emerging at the same time, ramping to high volume production.

Fan-Out WLP technology is emerging on both 200mm / 300mm infrastructures

Infineon is having a great sucess with its proprietary eWLB technology: the first FO-WLP wafers are mass produced on 200mm both at Infineon, STATS ChipPAC and ASE since 2009. Indeed, Fan-Out WLP is extending the general concept of Wafer Scale Packaging to new application categories, especially the ones with higher pin-counts and larger chip READ MORE >

FEATURED COMPANIES

  • 3D-Plus
  • Casio Micronics
  • Flip-chip International
  • LG Electronics
  • Panasonic
  • STMicroelectronics
  • MORE

Scope of the Report & Definitions
- Objectives of the report

Executive Summary

1 - Embedded die Packaging of active ICs and passive components
- Motivations and Drivers
- Applications & End-markets:
- Status of commercialization
- - Cell-phone & Consumer applications
- - Automotive applications
- - Medical applications
- 2009-2015 market forecasts for Embedded die packages
- - In Package shipments (Munits)
- - In Packaging revenues ($M)
- Supply chain emerging for embedded die packages
- - Players and positioning in the electronic value chain
- - Who is the most aggressive in the commercialization?
- - Who is doing what: partnership identified
- Technology flavors for embedded package
- - Chip first versus chip last?
- - Single die embedding versus SiP module?
> SiP multi-die integration
> Discrete passive integration
> Specific features integration (silicon interposers, holes,fluidic, hermetic cavities, etc…)
- - Challenges related to yield & supply chain
- Equt & Material Tool-Box for Embedded die
- Cost structure for Embedded packages manufacturing
- - Comparison with competitive package alternative that Embedded die technology is looking for direct replacement (QFN, BGA, WLCSP, SOT, PoP…)
- - Cost structure target of Embedded die for different application case (RFID, IPD, Power MOSFET / IGBT, DC/DC converters, PMU, Wireless Connectivity ICs, Digital Baseband, Memories, etc …)
- Conclusion on “sweets spots” for the introduction of Embedded die technology in the short / medium / long term
- - Global Roadmap for Embedded die

2 - Fan-Out WLP package technology development
- Motivations and market drivers
- - Thermal performance of FOWLP package compared to FC-BGA package solution
- Applications & status of commercialization
- 2009-2015 market forecasts for FOWLP type of packages
- - In Package shipments (Munits)
- - In Packaging revenues ($M)
- Supply chain emerging for FOWLP
- - Players and positioning in the electronic value chain
- - Who is the most aggressive in the commercialization?
- - Who is doing what: partnership identified
- FOWLP technologies & challenges
- - Who owns the IP in this space?
- - 1st generation versus 2nd generation FOWLP TMV “Through Mold Via” fabrication
- - “Panel size” manufacturing for future FO-WLP
- - Passive integration with FO-WLP technologies
- Equipment & Materials for FO-WLP
- - Challenges in new material’s selection and missing equipments
- Cost structure for FO-WLP manufacturing
- - Competitive package alternative that FOWLP technology is looking for direct replacement (FC-CSP, FC-BGA, PoP, etc…)
- - Cost structure for FOWLP by application (RFEM module, PoP digital module, PMU chip, wireless baseband SOC chip, etc…)
- Conclusion on “sweets spots” for introduction of FOWLP technology in short / medium long term
- - Global Roadmap for Fan-Out WLP

Conclusion- Application space for each generation of FO-WLP & Embedded die technology
- Impact of 3D TSV and silicon interposer technology concepts
- Global 3D Packaging development roadmaps mixing interposer, FO-WLP and Embedded die package technologies

Appendix
- Yole Developpement company presentation & services

- 3D-Plus
- ACET
- ADTEC Engineering
- Amkor
- ams
- Analog Devices
- AT&S
- Aptos
- Asahi Glass
- ASE
- ASM
- Atotech
- Broadcom
- Bosch
- Camtek
- Casio Micronics
- CIRETEC
- CMK
- Compass Technology
- CSR
- Datacon
- Daeduck
- Denso
- Dialog Semiconductor
- Dow Corning
- DuPont Electronics
- Dyconex
- Epic
- EVGroup
- Fico Molding
- Flip-chip International
- Fraunhofer IZM
- Freescale
- Fujitsu
- HD Microsystems
- Hynix Semiconductor
- Ibiden
- Imbera
- IME
- IMEC
- Infineon
- ipdia
- ITRI
- KYEC
- Leti
- Lintec
- LG Electronics
- Micron
- MicroChem
- Mitsui
- Murata
- Nagase ChemteX
- NANIUM
- NEC Electronics
- Nitto Denko
- Nokia
- NSC
- NXP
- Oki Electric
- ORC
- Panasonic
- PPT
- Qualcomm
- Renesas
- Rohm & Hass
- Rudolph technologies
- Samsung
- SEMCO
- Shinko Electric
- SPIL
- STATs chippa C
- ST Ericsson
- STMicroelectronics
- SPTS
- SMIC
- Shin-Etsu
- SÜSS Microtec
- Taiyo Yuden
- TDK
- Tessera
- Texas Instruments
- tok
- Tong Hsing
- Toray chemical
- Toray Engineering
- Toshiba
- Towa
- Triquint
- UMTC
- Unimicron
- Unovis
- UTAC
- Vertical Circuits
- Wolfson Microelectronics
- Yamada

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