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The Functional Verification of Electronic Systems
IEC Publications, March 2005, Pages: 450
The Functional Verification of Electronic Systems offers a comprehensive overview of functional verification from the points of view of leading experts currently at work in the electronic-design industry. As the size and complexity of modern chip designs have increased, the need for full and accurate functional verification during the design process has become still greater. Many companies are now realizing that verification is something they need as a core competence. However, the process of verification can devour a large portion of the effort devoted to a design project.
To address this, various techniques have emerged with the aim of improving the efficiency and effectiveness of the verification process. These include coverage, simulation, testbench automation, transaction-level modeling, and assertion-based verification. The Functional Verification of Electronic Systems examines past and current verification landscapes and assesses the technologies, languages, and methodologies in use today that will improve functional verification into the future.
The Features of this report are as follow:
- Provides insight into where the functional verification industry is headed in terms of new tools, new languages, and new methodologies and offers examples of how current challenges are being overcome
- Outlines the evolution of functional verification technologies and analyzes the benefits and drawbacks of each
- Presents an overview of current verification methodologies and languages, including SystemVerilog, PSL, SystemC, and e
- Explores how standards are fueling the development of new verification technology
Outlines key steps that a VC provider must take to verify the IP, the deliverables that must be provided along with the VC to the SoC team, and ways to leverage the VC verification in the context of the full chip
- Presents a bevy of verification plan ideas, tricks, and concepts that successful verification teams are using to tackle the ever-growing complexity of verifying a modern SoC Provides an overview of the different types of predictor models and shows how they are used within a verification flow
- Presents a high-level requirements specification methodology for applying pure formal verification in the verification flow
-Assesses the costs of design problems and the cost-effectiveness of lint tools for eliminating such problems
- Explores hardware/software co-verification and how it can be applied to various kinds of design and tool environments
-Discusses the evolution of coverage methodology as well as the benefits of including coverage techniques in the ASIC verification process
-Describes a chip-level, mixed-signal verification environment that combines analog and digital elements
- Explores more efficient means of generating tests and the writing of simulation test environments so that the simulator can automate the generation of stimulus to create new tests
Assesses the challenges of SoC debug and current efforts to automate it
- Presents strategies for successfully managing a 15+ million gate networking ASIC verification using sophisticated tools and methodologies
- Describes a modular approach to constructing a mixed-signal testbench environment using a reusable abstract layer of virtual test equipment implemented in VHDL for mixed-signal simulation
- Examines the use of assertion-based verification techniques to help accelerate the discovery and diagnosis of design flaws during functional verification
- Discusses methodological issues involved in formal property checking
Analyzes the various parts of the verification process for a highly configurable embedded processor
- Provides a comprehensive glossary of electronic-design industry terminology.
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