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DRAM Circuit Design: Fundamental and High-Speed Topics , 2nd Edition
John Wiley and Sons Ltd, Dec 2007, Pages: 421
This easy-to-read tutorial focuses on the chip designer rather than the user. It covers the transistor-level design of DRAM building blocks, including architecture and the array, voltage regulators and pumps, and peripheral circuits.
This book presents both standard and high-speed implementations in a balanced approach to help IC designers prepare for the future. It includes details of delay-locked loops (DLLs), digital phase-locked loops (DPLLs), output circuit paths including transmission lines, terminations, and protocols.
Author Info:
Brent Keeth is a Fellow in DRAM Design R&D at Micron Technology, Inc. His twenty-five years of industry experience spans radar systems, avionics components, communicationsystems, professional production and post-production equipment for the broadcast television industry, and solid-state memory. He holds over 400 U.S. and foreign granted or pending patents.
R. Jacob Baker, PhD, is an engineer, educator, and inventor. He has more than twenty years of engineering experience and holds over 200 granted or pending patents in integrated circuit design. Dr. Baker is the author of several circuit design books. For a detailed biography, see http://cmosedu.com/jbaker/jbaker.htm.
Brian Johnson is a Senior Design Engineer in DRAM Design R&D at Micron Technology, Inc. His research interests include asynchronous sequential circuits, clock synchronization circuits, and high-speed logic design. He holds over 60 granted or pending patents related to DRAM design and integrated circuit design.
Feng Lin, PhD, is a Senior Design Engineer in DRAM Design R&D at Micron Technology, Inc. His research interests include high-speed I/O circuits, PLL/DLL, and mixed-signal circuit design. Dr. Lin holds over 50 granted or pending patents related to DRAM and integrated circuit design.
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