- Language: English
- Published: July 2012
- Region: Spain
This product is currently not available for purchase.
Efficient and Scalable Cache Coherence for Chip Multiprocessors. Edition No. 1
- Published: January 2010
- Region: Global
- 196 Pages
- VDM Publishing House
Chip multiprocessors (CMPs) constitute the new trend for increasing the performance of future computers. In the near future, chips with tens of cores will become more popular. Nowadays, directory-based protocols constitute the best alternative to keep cache coherence in large-scale systems. Nevertheless, directory-based protocols have two important issues that prevent them from achieving better scalability: the directory memory overhead and the long cache miss latencies. This book focuses on these key issues. The first proposal is a scalable distributed directory organization that copes with the memory overhead of directory-based protocols. The second proposal presents the direct coherence protocols, which are aimed at avoiding the indirection problem of traditional directory-based protocols and, therefore, they improve applications' performance. Finally, a novel mapping policy for distributed caches is presented. This policy reduces the long access latency while lessening the number of off-chip accesses, leading to improvements in applications' execution time.
Alberto Ros received the MS and PhD degrees in computer science from the Universidad de Murcia, Spain, in 2004 and 2009, respectively. In 2005, he joined the Computer Engineering Department as a PhD student with a fellowship from the Spanish government. His research interests include cache coherence protocols and memory hierarchy designs.