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Viewing report
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Language-based Security for VHDL. Edition No. 1
VDM Publishing House, Aug 2009, Pages: 148
The need for reliable performance of computerised systems is well-known, yet the security verification of hardware systems is often none-existing or applied in an ad-hoc manner. Hence in this book it is investigated how language-based security techniques can be adapted and applied to hardware specifications. A novel policy language is presented for expressing permissible information flow using expressive constraints on the execution traces for programs. Based on the policy language a security property is proposed and shown to be a generalised intransitive non-interference condition. The means to verify the property is provided in the terms of a static information flow analysis. Practical implementations of embedded systems are vulnerable to side channel attacks. In particular timing channels have had a great impact on the security verification of algorithms for cryptography. In order to address this, another security property stating the absence of timing channels is presented. Again, verification is provided by a static analysis, which identifies the timing behaviour of a program.
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