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SATH: Simulated Annealing C code To FPGA Hardware compiler. Edition No. 1

Description:
A tool flow is presented for deriving accelerator
circuits on an FPGA
from ANSI C source code by exploring architecture
solutions that
conform to a preset template through scheduling and
mapping
algorithms. A case study carried out on simulated
annealing-based
scheduling software used for spacecraft systems is
explained. The goal
of the tool is the derivation of a design that
maximizes throughput
while minimizing footprint. Results obtained are
compared with a peer
C to RTL tool, a space-borne embedded processor and a
commodity
desktop processor for a variety of problems.
 
Author
Jonathan, Phillips.
Dr. Jonathan Phillips received his B.S. (Brigham Young
University, 2000), his M.S. and
Ph.D. in Electrical Engineering (Utah State University, 2004 and
2008). He is currently
employed at the USU Research Foundation, where he continues to
investigate real-
world applications for multi-FPGA data processing and
communications systems.

 
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SATH: Simulated Annealing C code To FPGA Hardware compiler. Edition No. 1

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