It is not a trivial task to fabricate displays on plastic and significant challenges arise when clear plastic is used to replace glass as the display substrate. The trend has been to reduce the deposition temperature of amorphous silicon thin-film transistors (a-Si:H TFTs) in the display backplanes on plastic but that results in a-Si:H TFTs with poor stability under gate-bias stress. The goal of this thesis work has been to develop a high-temperature TFT process at 300C on plastic to enable stable backplanes that are competitive with backplanes fabricated on glass. We have investigated back channel passivated and back-channel cut a-Si:H TFTs fabricated on plastic at 300C and have obtained TFTs with a stability under gate-bias stressing equivalent to that of TFTs in commercial backplanes on glass. Next, we looked at ways to mitigate the impact of misalignment at high temperatures that was caused by large strains built into the substrate by device fabrication. We did this by implementing stress control and by developing self-alignment methods between the gate, the channel passivation and the source-drain terminals.
Dr Kunigunde Cherenack was born in Cape Town, South Africa. She attended the University of Stellenbosch where she received her Bachelor and Master of Science in Engineering. She graduated from Princeton University in January 2009 and is currently employed as a post-doctorate researcher at ETH Zürich.