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Architectural Optimizations in Multi-Core Processors. Edition No. 1
VDM Publishing House, Nov 2008, Pages: 144
The quest for greater computational power is
never-ending. Recently, the architectural trend has
shifted from improving single-threaded application
performance to improving multi-threaded application
performance. Thus, multi-core processors have been
increasingly popular. To achieve concurrent execution
of threads on multi-core processors, applications
must be explicitly restructured to exploit
parallelism, either by programmers or compilers.
However, conventional parallel programming models may
introduce overhead due to synchronization and
communications among threads in multi-threaded
applications. This book presents three architectural
optimizations to improve thread-based synchronization
and communications support in multi-core processors.
Register-Based Synchronization (RBS) uses hardware
registers efficiently to provide synchronization
support in multi-core processors. Prepushing is a
software controlled data forwarding technique to
provide communications support in multi-core
processors. Software Controlled Eviction (SCE)
improves shared cache communications by placing
shared data in shared caches.
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