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Viewing report
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Gate Stacks with High-k Dielectrics and Metal Electrodes. Edition No. 1
VDM Publishing House, June 2009, Pages: 124
Continuing to scale down the transistor size makes
the adoption of high-k gate dielectrics and metal
electrodes necessary. However, there are still a lot
of problems with high-k transistors such as
Fermi-level pinning (FLP), which affects flatband
voltage ?Vfb?and threshold voltages (Vth) directly.
This book summarizes three FLP mechanisms in gate
stacks with high-k dielectrics and metal electrodes?
a dipole formation through (1) the mechanism of
oxygen vacancy formation in a high-k dielectric
layer; (2) the hybridization between a metal gate and
a high-k dielectric layer; and (3) the interaction
between an interfacial SiO2 layer and a high-k
dielectric layer. This book focuses on the study of
FLP and dipoles induced by capping a thin lanthanide
oxide layer on a gate stack with a Hf-based high-k
dielectric. By examining Vfb shifts in specially
designed gate stacks, it is concluded that the
negative Vfb shift is due to a dipole formation at
the interface between the interfacial SiO2 layer and
a lanthanide silicate layer. The Vfb shifts by other
two FLP mechanisms are also studied. The book is very
useful for those who are interested in FLP and Vth
tuning in high-k transistors.
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