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Viewing report
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A parallel Architecture for Motion Estimation using H.264/AVC standard. Edition No. 1
VDM Publishing House, Feb 2010, Pages: 244
Motion Estimation Architecture for parallel execution using FPGA based systems. A novel architecture proposed reduces execution time and improves throughput for Motion Estimation. This Architecture is verifed experimentally on a Xilinx based FPGA system. This was a result of ongoing research project at San Francisco State University California and a thesis for my Masters Degree in Elecrical Engineering.
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