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3D Integration for VLSI Systems
Pan Stanford Publishing Pte. Ltd, Sep 2011, Pages: 377
Three-dimensional (3D) integration is identified as a possible avenue for continuous performance growth in integrated circuits (IC) as the conventional scaling approach is faced with unprecedented challenges in fundamental and economic limits. Wafer level 3D IC can take several forms, and they usually include a stack of several thinned IC layers that are vertically bonded and interconnected by through silicon via TSV. There is a long string of benefits that one can derive from 3D IC implementation such as form factor, density multiplication, improved delay and power, enhanced bandwidth, and heterogeneous integration.
This book presents contributions by key researchers in this field, covering motivations, technology platforms, applications, and other design issues.
Key Features:
- Chapters are contributed by leading researchers in the field of 3D IC from academia, research institutes, and industry.
- A wide range of topics are covered, including background, technology platforms, applications, status, and outlook to provide the most comprehensive coverage of the field.
- Content is organized in a systematic flow of standalone chapters for easy reference.
Readership
Researchers and practicing engineers who are interested in enabling technology platforms (e.g., wafer bonding, TSV) and applications in the emerging field of 3D integration.
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