Nanometer Frequency Synthesis Beyond the Phase-Locked Loop. IEEE Press Series on Microelectronic Systems
- Language: English
- 344 Pages
- Published: September 2012
The latest frequency synthesis techniques, including sigma-delta, Diophantine, and all-digital
Sigma-delta is a frequency synthesis technique that has risen in popularity over the past decade due to its intensely digital nature and its ability to promote miniaturization. A continuation of the popular Frequency Synthesis by Phase Lock, Second Edition, this timely resource provides a broad introduction to sigma-delta by pairing practical simulation results with cutting-edge research. Advanced Frequency Synthesis by Phase Lock discusses both sigma-delta and fractional-n—the still-in-use forerunner to sigma-delta—employing Simulink® models and detailed simulations of results to promote a deeper understanding.
After a brief introduction, the book shows how spurs are produced at the synthesizer output by the basic process and different methods for overcoming them. It investigates how various defects in sigma-delta synthesis contribute to spurs or noise in the synthesized signal. Synthesizer configurations are analyzed, and it is revealed how to trade off the various noise sources by choosing loop parameters. Other sigma-delta synthesis architectures are then reviewed.
The Simulink simulation models that provided data for the preceding discussions are described, providing guidance in making use of such models for further exploration. Next, another method for achieving wide loop bandwidth simultaneously with fine resolution—the Diophantine Frequency Synthesizer—is introduced. Operation at extreme bandwidths is also covered, further describing the analysis of synthesizers that push their bandwidths close to the sampling-frequency limit. Lastly, the book reviews a newly important technology that is poised to become widely used in high-production consumer electronics—all-digital frequency synthesis.
Detailed appendices provide in-depth discussion on various stages of development, and many related resources are available for download, including Simulink models, MATLAB® scripts, spreadsheets, and executable programs. All these features make this authoritative reference ideal for electrical engineers who want to achieve an understanding of sigma-delta frequency synthesis and an awareness of the latest developments in the field. SHOW LESS READ MORE >
Symbols List and Glossary.
1.1 Phase-Locked Synthesizer.
1.2 Fractional-N Frequency Synthesis.
1.3 Representing a Change in Divide Number.
1.5 Representing Phase Noise.
1.6 Phase Noise at the Synthesizer Output.
1.7 Observing the Output Spectrum.
2 Fractional-N and Basic EA Synthesizers.
2.1 First-Order Fractional-N.
2.2 Second-Order Fractional-N.
2.3 Higher-Order Fractional-N.
2.4 Spectrums with Constant Sampling Rate.
2.5 Summary of Spectrums.
3 Other Spurious Reduction Techniques.
3.1 LSB Dither.
3.2 Maximum Sequence Length.
3.3 Shortened Accumulators and Lower Primes.
3.4 Long Sequence.
4 Defects in EA Synthesis.
4.1 Noise Models.
4.2 Levels of Other Noise in EA Synthesizers.
4.3 Noise Sources, Equivalent Input Noise.
4.4 Discrete Sidebands.
5 Other EA Architectures.
5.4 Quantizer Offset.
5.6 Cancellation of Quantization Noise in the General Modulator.
5.7 Fractional Swallows.
5.8 Hardware Reduction.
6.9 Adapting a Model.
6.12 MASH modulator scripts.
6.14 Other Methods.
7 Diophantine Synthesizer.
7.1 Two-Loop Synthesizer.
7.2 Multi-Loop Synthesizers.
7.3 MATLAB Scripts.
7.4 Signal Mixing.
7.5 Reference-Frequency Coupling.
7.6 Center Frequencies.
8 Operation at Extreme Bandwidths.
8.1 Determining the Effects of Sampling.
8.2 A Particular Case.
8.3 When Are Sampling Effects Important?
8.4 Computer Program.
8.5 Sampling Effects in S? Synthesizers.
9 All-Digital Frequency Synthesizers.
9.1 The Flying Adder Synthesizer.
9.2 The ADPLL Synthesizer.
Appendix A All Digital.
A.1 Flying Adder Circuits.
A.2 ADPLL Synthesizer.
Appendix C Fractional Cancellation.
C.1 Modulator Details.
C.2 First Accumulator.
C.3 Second Accumulator.
C.4 Additional Accumulators.
C.5 Accumulator Without Input Register.
Appendix E Excess PPSD.
E.1 Development of Eq.
E.2 Approximating kp.
E.3 Approximation in Eq.
Appendix F References to FS2.
Appendix G Using Gsmp1.
G.1 Open-Loop Transfer Function.
G.2 Close-Loop Responses.
G.3 Saving Results.
G.4 Version Number.
G.5 Example Session.
G.6 Generating Analysis Plots.
G.7 Verification of Gardner’s Stability Limits.
G.8 The Nyquist Plot.
Appendix H Sample and Hold Circuit.
H.1 Transient Performance.
H.2 Filter Capacitor Before Sampler.
Appendix L Loop Response.
L.1 Primary Loop.
L.2 Damped Loop.
Appendix M MASH PSD.
M.1 MASH Modulator, First Stage.
M.2 MASH Modulator, Second-Order.
M.3 MASH Modulator, Higher Order.
M.5 Some Parameters of Sf.
M.6 Previous Development.
M.7 Some MASH Modulator Characteristics.
M.8 Characteristics of MATLAB Scripts mashone and mashall_.
Appendix N Sampled Noise.
N.1 Case 1, Wn fref.
N.2 Case 2, 1/T >> Wn >> fref.
N.3 Case 3, Wn >> 1/T >> fref.
N.4 Variance of Sampled Noise (1/T >> fref).
N.5 Convolution of PSDs.
N.6 Representing Squared PSDs.
Appendix O Oscillator Spectrums.
Appendix P Phase Detectors.
Appendix Q Quantization PPSD.
Q.1 Development of Eq.
Q.3 New Synthesized Frequency.
Q.4 Loop Response.
Q.5 Verification of the Effect of Sampling on the Loop.
Appendix R Reference-Frequency Spurs.
R.1 Leakage Current.
R.2 Pulse Offset.
R.3 EA Modulation.
R.4 Effect of EA Modulation on Pulse Offset Spurs.
R.5 Effect of EA Modulation on Leakage Spurs.
R.6 Effects of Resampling.
Appendix S Spectrum Analysis.
S.2 The Spectrum Analyzer.
S.3 The Window Function.
S.4 Density and Discrete Spurs.
S.5 Control Parameters.
S.6 Frequency Conversion in an Analyzer.
S.7 Displaying L, FPSD, and PPSD.
S.8 Spectral Overlaps.
S.9 Anomalous Spurs.
Appendix T Toolboxes.
Appendix U Noise Produced by Charge-Pump Current Unbalance (Mismatch).
Appendix W Getting Files from the Wiley Internet Site.
Appendix X Some Tables.
X.1 Accumulator Shortening.
X.2 Sequence Lengths.
William F. Egan, PhD, is a lecturer in electrical engineering at Santa Clara University, California. Formerly, he was a principal engineer at TRW ESL and a senior technologist at GTE Government Systems.