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Advanced IC Packaging Technologies, Materials, and Markets, 2011 Edition Product Image

Advanced IC Packaging Technologies, Materials, and Markets, 2011 Edition

  • Published: November 2011
  • Region: World
  • 270 Pages +
  • New Venture Research

FEATURED COMPANIES

  • Amkor Technology
  • Elpida Memory
  • Imec
  • Micro Systems Engineering
  • Powertech Technology
  • STMicroelectronics
  • MORE

Despite a global recession, the demand for handheld portable products remains strong. To continue to meet the ever-increasing needs for higher bandwidth, IC packaging technologies are continually being pushed to the limit. This report details the advances in those limits. New Venture Research (NVR) in its report, Advanced IC Packaging Technologies, Materials, and Markets, 2011 Edition , uses information from IC packaging industry insiders to present the most realistic forecasts available regarding advanced IC packaging. Throughout the report, the latest advanced packaging products, services, and research from numerous companies and organizations are described.

Chapter 3, Stacked Packages, explains the basics of this critical packaging technology, along with a sampling of the latest products. Forecasts include units, prices, packaging revenue, package types, device types, first-level interconnection, and applications.

Chapter 4, TSV Market (3D and 2.5D stacking) is covered in depth, including various methods of connecting the devices, specific company applications, and numerous examples of the latest new products and processes. Unit projections are forecast and an examination READ MORE >

Chapter 1: Introduction

Chapter 2: Executive Summary

Chapter 3: Stacked Packages
- Types of Stacked Packages
- The Ins and Outs of Stacked Packages
- Interconnection
- Stacked Package as a Multicomponent Package
- Wafer Thinning
- End Markets and Application Trends
- New Product Introductions
- Stacked Package Forecasts
- Stacked Packages by Application
- End Markets for Stacked Packages
- Potential Markets
- Stacked Packages by Device Type
- Stacked Packages by Interconnection

Chapter 4: Through Silicon Via (TSV) Market
- Overview
- Creating the Vias
- Issues
- 3D Die-Stacking Technology Requirements
- 2.5D - Silicon Interposers and Microbumps
- Wafer-to-Wafer Bonding
- Die-to-Wafer Bonding
- Die-to-Die Bonding
- Via First, Middle, or Last Technology
- Via Etching and Filling
- Specific Company Applications
- Companies with TSV Designs
- New Product Highlights
- Advances in Test
- Moving Forward
- Industry Consortiums
- Market Potential
- Forecasts for 2.5D and 3D

Chapter 5: System in Package (SiP)
- Solutions
- Overview
- New Product Introductions/Highlights
- SiP Forecasts
- Summary
- SiPs by Application
- SiPs by Device Type
- SiPs by Interconnection

Chapter 6: Fan-in QFN Packages
- Overview
- New Product Introductions
- Market Forecasts

Chapter 7: Wafer-Level Packages including Fan-out
- WLPs
- Wafer-Level Package Overview
- New Product / Process Introductions
- Market Forecasts for WLP
- Forecasts by Product
- Forecasts by Pitch
- Forecasts of Fan-out WLP

Chapter 8: Interconnection, Wire Bond, Flip Chip and
- Bumping
- Interconnection Overview
- Wire Bonding
- Flip Chip
- TAB
- Wafer-Bumping and Process Overview
- Alternatives to Solder
- Product Highlights
- Flip Chip Applications
Forecasts for:
- Interconnect by Package Units
- Wire Bond Package Units and Materials
- Flip Chip
- Flip Chip Bumps
- UBM Process Techniques
- Total Wire Bond and Flip Chip

Chapter 9: Substrates
- Overview
- Ceramic
- Laminate
- HDIS
- Flex Tape
- Embedded Passives
- Thermal Substrates
- Product Highlights
- Forecasts
- Units by Pitch
- Units, Area, Revenue by Package Family
- Units, Area, Revenue by Material

Chapter 10: State of the Industry and Applications for
- Mobile Devices
- Overview of Current Market Status
- Mobile Electronic Applications for IC device by Product
- Group
- Total IC for each Product Category
- Total IC Revenue

Handheld Electronics Require Advanced IC Packages
The demand for portable Internet connectivity devices such as cell phones, tablets, GPS devices, MP3 players, and more is very strong, in spite of poor economic times. What these items have in common is that they all pack an enormous amount of functionality into a very small space. To achieve this feat, these products must utilize more advanced packaging methods for the ICs inside the products, as it is the IC packages that hold the footprint to the PCB and thus determine the size of the PCB and, ultimately, the size of the final product. The packaging method of the chip also determines the speed and performance of that chip, as well as its battery consumption.

These devices are fueling demand for advanced IC packaging technologies such as system in package (SiP), stacked packages, fan-in QFNs, fan-out WLPs, and interconnection styles of 3-D and 2.5-D through-silicon vias (TSVs) and flip chip.

Stacked Packages
Stacked packages are essentially a vertical multichip package. They come in many forms, including die stacks, package on package (PoP), package in package (PiP), TSOP stacks, QFNs, MCMs, and WLPs. Now found in all cell phones, stacked packages are in a high-demand market. Stacked package revenue will experience a 10 percent CAGR through 2015.

Through-Silicon Vias (TSVs)/3-D interconnect
Using 3-D interconnection with TSVs creates a die stack with the shortest interconnection distance, enhancing the characteristics of high speed, low power consumption, reduced parasitics, and small form factor. This interconnection style utilizes vias that go through the silicon to electrically connect one die to the next in a vertical stack, in place of wire bonds or other forms of connection. The identified potential markets for TSVs will climb from 35 billion units in 2010 to over 54 billion in 2015.

System in Package (SiP)
SiPs are a functional block, a system of electronics that combines functional units together onto a single substrate to enable the shortest electrical distance between parts for superior performance. This reduces the amount of traces going into and out of the package, enabling a more simplistic PCB for the final product and potentially reducing system costs. Revenue for SiPs will expand at a 5.4 percent CAGR through 2015.

Fan-In QFNs
To increase the reach of the QFN package, this involves extending the number of rows of leads from the usual one to two or three rows. This allows the number of package leads to extend into the hundreds, up from generally fewer than 50. Although the number of fan-in QFNs assembled currently is quite small, the potential is huge, with a projected CAGR of 63.1 percent for revenue through 2015.

Fan-Out WLPs
Reconfigured or fan-out wafer-level packages (WLPs) were introduced in 2006. After devices are manufactured on a wafer, the devices are sawn and transferred on a carrier to another larger wafer that has gaps between die, which are filled with overmold material that also coats the back side of the devices for protection. This allows for a larger surface on which to extend a redistribution layer, thus allowing for far more I/Os than would be possible on the original smaller WLP surface. Solder balls or bumps can be added to this surface for interconnection to a printed circuit board. Fan-out WLPs are expected to have a CAGR of 15.9 percent for revenue through 2015.

Applications for Advanced IC Packages
Cellular handsets are the primary handheld electronic gadget that everyone wants to own. Their use is spreading around the world, especially in territories too vast to support wired communication lines. Cellular handsets are growing at an 8.5 percent CAGR between 2011 and 2015, and smart phones, a subset of total cellular handsets, are growing at a 15.2 percent CAGR. Such rates definitely exceed that of the economy as a whole.

- Amkor Technology
- Avago Technologies
- Brewer Science
- Cadence Design Systems
- Dow Chemical
- Elpida Memory
- Endicott Interconnect Technologies
- EPWorks
- FlipChip International
- Fraunhofer Institute for Reliability and Microintegration
- Fujikura Ltd.
- Georgia Institute of Technology, 3D Systems Packaging Center
- IBM Corp.
- IBM T.J. Watson Research Center
- Imec
- Infineon Technologies
- ITRI
- KSG Leiterplatten
- Mentor Graphics
- Micron Technology
- Micro Systems Engineering
- NAMICS
- Nanium
- Nokia Japan
- Pac Tech Packing Technologies
- Powertech Technology
- Renesas Electronics Corp.
- Rochester Institute of Technology
- Samsung
- Sandia National Laboratory
- SphereTek
- SPTS, SPP Process Technology Systems
- STATS ChipPAC
- STMicroelectronics
- Sumitomo Bakelite
- SunRay Scientific
- Suss MicroTec
- Technical University Berlin
- Texas Instruments
- Tokyo Ohka Kogyo
- University Erlangen-Nuremberg, Institute for Manufacturing Automation and Production Systems
- UTAC
- Wacker
- Xilinx
- Zymet

Format Properties
Electronic (PDF) The report will be emailed to you. The report is sent in PDF format. This is a single user license, allowing one specific user access to the product.
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