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VLSI Test Principles and Architectures

  • ID: 1765632
  • Book
  • 808 Pages
  • Elsevier Science and Technology
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This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume.

- Most up-to-date coverage of design for testability. - Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. - Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.

Please Note: This is an On Demand product, delivery may take up to 11 working days after payment has been received.
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Chapter 1
Chapter 2
Design for Testability
Chapter 3
Logic and Fault Simulation
Chapter 4
Test Generation
Chapter 5
Logic Built-In Self-Test
Chapter 6
Test Compression
Chapter 7
Logic Diagnosis
Chapter 8
Memory Testing and Built-In Self-Test
Chapter 9
Memory Diagnosis and Built-In Self-Repair
Chapter 10
Boundary Scan and Core-Based Testing
Chapter 11
Analog and Mixed-Signal Testing
Chapter 12
Test Technology Trends in the Nanometer Age
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Wang, Laung-Terng
Laung-Terng Wang, Ph.D., is founder, chairman, and chief executive officer of SynTest Technologies, CA. He received his EE Ph.D. degree from Stanford University. A Fellow of the IEEE, he holds 18 U.S. Patents and 12 European Patents, and has co-authored/co-edited two internationally used DFT textbooks- VLSI Test Principles and Architectures (2006) and System-on-Chip Test Architectures (2007).
Wu, Cheng-Wen
Wen, Xiaoqing
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