The feature sizes of microelectronic devices have entered the deep submicron regime. The process integration and structure-properties control of the multilevel metal circuitry demand an interdisciplinary interaction and understanding between manufacturing and research. To realize the vision presented in the national technology road map, material and technological challenges will need to be overcome. For example Cu conductor and its barrier metals and low-dielectric constant insulators are at issue. For materials processing, chemical-mechanical planarization and low-temperature filling of high-aspect ratio vias are challenges. For materials examination, the metrology of submicron structures is nontrivial and for materials reliability, the interplay among multiple driving forces and the response in small-dimension microstructures are intriguing. These issues are the focus of this book from MRS. Topics include: road map, technology and metrology of submicron device structures; reliability issues for Cu metallization; Al interconnects and vias; barrier metal; interlevel low-K dielectrics and contact to Si and compound semiconductors.
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