• ID: 2170278
  • Book
  • 474 Pages
  • John Wiley and Sons Ltd
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Interest in latchup is being renewed with the evolution of complimentary metal–oxide semiconductor (CMOS) technology, metal–oxide–semiconductor field–effect transistor (MOSFET) scaling, and high–level system–on–chip (SOC) integration.

Clear methodologies that grant protection from latchup, with insight into the physics, technology and circuit issues involved, are in increasing demand.

This book describes CMOS and BiCMOS semiconductor technology and their sensitivity to present day latchup phenomena, from basic over–voltage and over–current conditions, single event latchup (SEL) and cable discharge events (CDE), to latchup domino phenomena. It contains chapters focusing on bipolar physics, latchup theory, latchup and guard ring characterization structures, characterization testing, product level test systems, product level testing and experimental results. Discussions on state–of–the–art semiconductor processes, design layout, and circuit level and system level latchup solutions are also included, as well as:

  • latchup semiconductor process solutions for both CMOS to BiCMOS, such as shallow trench, deep trench, retrograde wells, connecting implants, sub–collectors, heavily–doped buried layers,  and buried grids from single– to triple–well CMOS;
  • practical latchup design methods, automated and bench–level latchup testing methods and techniques, latchup theory of logarithm resistance space, generalized alpha  (a) space, beta (b) space, new latchup design methods connecting the theoretical to the practical analysis, and;
  • examples of  latchup computer aided design (CAD) methodologies, from design rule checking (DRC) and logical–to–physical design,  to new latchup CAD methodologies that address latchup for internal and external latchup on a local as well as global design level.

Latchup acts as a companion text to the author s series of books on ESD (electrostatic discharge) protection, serving as an invaluable reference for the professional semiconductor chip and system–level ESD engineer. Semiconductor device, process and circuit designers, and quality, reliability and failure analysis engineers will find it informative on the issues that confront modern CMOS technology.  Practitioners in the automotive and aerospace industries will also find it useful. In addition, its academic treatment will appeal to both senior and graduate students with interests in semiconductor process, device physics, computer aided design and design integration.

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About the Author.



Chapter 1 CMOS Latchup.

1.1 CMOS Latchup.

1.2 Fundamental Concepts of Latchup Design Practice.

1.3 Building a CMOS Latchup Strategy.

1.4 CMOS Latchup Technology Migration Strategy.

1.5 Key Metrics of Latchup Design Practice.

1.6 CMOS Latchup Technology Trends and Scaling.

1.7 Key Developments.

1.8 Latchup Failure Mechanisms.

1.9 CMOS Latchup Events.

1.10 Electrostatic Discharge Sources.

1.11 Single Event Latchup.

1.12 Summary and Closing Comments.



Chapter 2 Bipolar Transistors.

2.1 The Bipolar Transistor and CMOS Latchup.

2.2 Bipolar Transistor.

2.3 Recombination Mechanisms.

2.4 Photon Currents in Metallurgical Junctions.

2.5 Avalanche Breakdown.

2.6 Vertical Bipolar Transistor Model.

2.7 Lateral Bipolar Transistor Models.

2.8 Lateral Bipolar Transistor Models with Electric Field Assist.

2.9 Lateral Bipolar Transistor Models Nonuniform Vertical Profile.

2.10 Triple–Well Bipolar Transistor Models Lateral and Vertical Contributions.

2.11 Merged Triple–Well Bipolar Models.

2.12 Summary and Closing Comments.



Chapter 3 Latchup Theory.

3.1 Regenerative Feedback.

3.1.1 Regenerative Feedback without Shunt Resistors and Alpha Representation.

3.2 Latchup Criterion with Emitter Resistance.

3.3 Holding Point Conditions.

3.4 Resistance Space.

3.5 Beta Space.

3.6 CMOS Latchup Differential Tetrode Condition.

3.7 CMOS Latchup Differential Holding Current Relationship.

3.8 CMOS Latchup Differential Holding Voltage Relationship.

3.9 CMOS Latchup Differential Resistance Relationship.

3.10 Differential Generalized Alpha Space Relationship.

3.11 High–Level Injection.

3.12 Transient Latchup.

3.13 External Latchup.

3.14 Alpha Particle Induced Latchup.

3.15 Summary and Closing Comments.



Chapter 4 Latchup Structures, Characterization and Test.

4.1 Guard Rings.

4.2 Latchup Characterization Structures Single– and Dual–Well CMOS PNPN  Test Structures.

4.3 Latchup Characterization Basic Triple–Well pnpn Latchup Test Structures.

4.4 Latchup Characterization Techniques pnpn Structures with Deep Trench.

4.5 Latchup Characterization and Testing Nonautomated Test Systems and Methodology.

4.6 Latchup Characterization and Testing Automatic Test Systems.

4.7 Latchup Characterization Wafer–Level Test Procedures.

4.8 Latchup Characterization Techniques Wafer–level Transmission Line Pulse Methodology.

4.9 Latchup Characterization Transient Latchup.

4.10 Guard Ring Characterization.

4.11 Latchup Failure Analysis Techniques.

4.12 Summary and Closing Comments.



Chapter 5 CMOS Latchup Process Features and Solutions Dual–Well and Triple–Well CMOS.

5.1 CMOS Semiconductor Process Solutions and CMOS Latchup.

5.2 Substrates.

5.3 n–Wells.

5.4 p–Well.

5.5 pþ/nþ Scaling.

5.6 Isolation and Latchup.

5.7 Silicide.

5.8 Triple Well.

5.9 High–Dose Buried Layer.

5.10 Future Concepts.

5.11 Summary and Closing Comments.



Chapter 6 CMOS Latchup Process Features and Solutions Bipolar and BiCMOS Technology.

6.1 CMOS Latchup in Bipolar and RF BiCMOS Technology.

6.2 Substrates High–Resistance Substrates.

6.3 Subcollectors.

6.4 Alternative Isolation Concepts.

6.5 Trench Isolation (TI).

6.6 Deep Trench.

6.7 Triple–Well and BiCMOS Processes Integration.

6.8 Heavily Doped Buried Layer Implant and BiCMOS Technology.

6.9 Summary and Closing Comments.



Chapter 7 CMOS Latchup Circuits.

7.1 Table of Circuit Interactions.

7.2 Intrabook Latchup Mechanisms.

7.3 Interbook Latchup Mechanisms.

7.4 Circuit Solutions Input Circuit.

7.5 Power Supply Concepts.

7.6 Latchup Circuit Solutions Power Supply to Power Supply Sequencing Circuitry.

7.7 Overshoot and Undershoot Clamp Networks.

7.8 Passive and Active Guard Rings.

7.9 Triple–Well Noise and Latchup Suppression Structures.

7.10 System–Level Issues.

7.11 Summary and Closing Comments.



Chapter 8 Latchup Computer Aided Design (CAD) Methods.

8.1 Latchup CAD Rules.

8.2 Design Rule Checking.

8.3 Computer–Aided Design Extraction Methodologies Searching for the pnpn.

8.4 CAD Extraction Methods Searching for the Guard Rings.

8.5 Latchup Extraction Methods and Tools.

8.6 Latchup CAD Simulation.

8.7 Summary and Closing Comments.




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Steven H. Voldman is an IEEE Fellow for ′Contributions in ESD Protection in CMOS, Silicon on Insulator and Silicon Germanium Technology′. He has a B.S. engineering science from University of Buffalo (1979), a first M.S. EE (1981) from Massachusetts Institute of Technology (MIT), a second EE degree (engineering degree) from MIT,a M.S. in engineering physics (1986) and a Ph.D. EE (1991) from University of Vermont under IBM′s Resident Study Fellow Program.

Since 1984, Voldman has provided experimental research, invention, chip design integration, circuit design, customer support and strategic planning for ESD and latchup. His latchup and ESD work consist of pioneering work on advanced CMS and BiCMOS semiconductor processing, and presently he is working on RF CMOS, RF BiCMOS silicon germanium (SiGe) technology, image processing and high–voltage smart power technology.

Dr Voldman has written over 150 technical papers between 1982 and 2007. He is a recipient of over 160 issued US patents and 80 US patents are pending, in the area of ESD and CMOS latchup, Dr Voldman is an author of the John Wiley & Sons ESD book series – the first book, ESD: Physics and Devices; the second book, ESD: Circuits and Devices; and the third book, ESD: RF Technology and Circuits – as well as a contri8butor to the book, Silicon Germanium: Technology, Modeling and Design. Dr. Voldman was chairman of the SEMATECHESD Working Group from 1995 to 2000, to establish a national strategy for ESD in the United Sates; this group initiated ESD technology  benchmarking strategy, test structures and commercial test system strategy. Dr Voldman was also part  of the SEMATECH vertical modulated well PTAB in 1992 that focused on MeV implantation of latchup. He is a member of the ESD Association Board of Directors, ESDA Education Committee, as well ESD Standards Chairman for Transmission Line Pulse (TLP) and Very Fast TLP (VF–LP) testing committee. He has served on various Symposia internationally from technical program committee to tutorials on ESD and latchup – EOS/ESD Symposium, International Reliability Physics (IRPS), Taiwan ESSD Symposium (T–ESDC), International Conference on Electromagnetic Compatibility (ICEMAC), International Physical and Failure Analysis (IPFA) Symposium and Bipolar/BiCMOS Circuit Technology Meeting (BCTM).

Steve Voldman Initiated the ′ESD on Campus′ program to bring ESD lectures and interaction to university faculty and students internationally and has provided lectures in the United States, Europe, Taiwan, Singapore, Malaysia, Philippines, China and Thailand. Dr. Voldman received the ESD Association Outstanding Contribution Award in 2007.

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