The book also covers system level design of Multi Processor System on Chip (MPSoC); a consideration of different design methodologies including Network on Chip (NoC) and Kahn Process Network (KPN) based connectivity among processing elements. A special emphasis is placed on implementing streaming applications like a digital communication system in HW. Several novel architectures for implementing commonly used algorithms in signal processing are also revealed. With a comprehensive coverage of topics the book provides an appropriate mix of examples to illustrate the design methodology.
- A practical guide to designing efficient digital systems, covering the complete spectrum of digital design from a digital signal processing perspective
- Provides a full account of HW building blocks and their architectures, while also elaborating effective use of embedded computational resources such as multipliers, adders and memories in FPGAs
- Covers a system level architecture using NoC and KPN for streaming applications, giving examples of structuring MATLAB® code and its easy mapping in HW for these applications
- Explains state machine based and Micro–Program architectures with comprehensive case studies for mapping complex applications
1.2 Fueling the Innovation: Moore s Law.
1.3 Digital Systems.
1.4 Examples of Digital Systems.
1.5 Components of the Digital Design Process.
1.6 Competing Objectives in Digital Process.
1.7 Synchronous Digital Hardware Systems.
1.8 Design Strategies.
2. Using a Hardware Description Language.
2.2 About Verilog.
2.3 System Design Flow.
2.4 Logic Synthesis.
2.5 Using the Verilog HDL.
2.6 Four Levels of Abstraction.
2.7 Verification in Hardware Design.
2.8 Example of a Verification Setup.
3. System Design Flow and Fixed–Point Arithmetic.
3.2 System Design Flow.
3.3 Representations and Numbers.
3.4 Floating–point Format.
3.5 Qn.m Format for Fixed–point Arithmetic.
3.6 Floating–Point to Fixed–Point Conversion.
3.7 Block Floating–Point Format.
3.8 Forms of Digital Filter.
4. Mapping on Fully Dedicated Architecture.
4.2 Discrete Real–Time Systems.
4.3 Synchronous Digital Hardware Systems.
4.4 Kahn Process Network.
4.5 Methods of Representing DSP Systems.
4.6 Performance Measures.
4.7 Fully Dedicated Architecture.
4.8 DFG to HW Synthesis.
5. Design Options for Basic Building Blocks.
5.2 Embedded Processors and Arithmetic Units in FPGAs.
5.3 Instantiation of Embedded Blocks.
5.4 Basic Building Blocks: Introduction.
5.6 Barrel Shifter.
5.7 Cary Save Adder and Compressors.
5.8 Parallel Multipliers.
5.9 Two s Complement Signed Multiplier.
5.10 Compression Trees for Multi–operand Addition.
5.11 Algorithm Transformations for CSA.
6. Multiplier–less Multiplication by Constants.
6.2 Canonic Sign Digit Representation.
6.3 Minimum Signed Digit Representation.
6.4 Multiplication by Constant in Signal Processing Algorithm.
6.5 Optimized DFG Transformation.
6.6 Fully Dedicated Architecture for Direct–form FIR Filter.
6.7 Complexity Reduction.
6.8 Distributed Arithmetic.
6.9 FFT Architecture using FIR Filter Structure.
7. Pipelining, Retiming, Look–ahead Transformation and Polyphase Decomposition.
7.2 Pipelining and Retiming.
7.3 Digital Design of Feedback Systems.
7.4 C–slow Retiming.
7.5 Look–ahead Transformation for IIR filters.
7.6 Look–ahead Transformation for Generalized IIR Filters.
7.7 Polyphase Structure for Decimation and Interpolation Applications.
7.8 IIR Filter for Decimation and Interpolation.
8. Unfolding and Folding Architectures.
8.3 Sampling Rate Considerations.
8.4 Unfolding Techniques.
8.5 Folding Techniques.
8.6 Mathematical Transformation for Folding.
8.7 Algorithmic Transformation.
9.Designs based on Finite State Machines.
9.2 Examples of Time–shared Architecture Design.
9.3 Sequencing and Control.
9.4 Algorithmic State Machine Representation.
9.5 FSM Optimization for Low Power and Area.
9.6 Designing for Testability.
9.7 Methods for Reducing Power Dissipation.
10. Micro–programmed State Machines.
10.2 Micro–programmed Controller.
10.3 Counter–based State Machine.
10.4 Subroutine Support.
10.5 Nested Subroutine Support.
10.6 Nested Loop Support.
11. Micro–programmed Adaptive Filtering Applications.
11.2 Adaptive Filters Configurations.
11.3 Adaptive Algorithms.
11.4 Channel Equalizer using NLMS.
11.5 Echo Canceller.
11.6 Adaptive Algorithms with Micro–programmed State Machines.
12 CORDIC–based DDFS Architectures.
12.2 Direct Digital Frequency Synthesizer.
12.3 Design of a Basic DDFS.
12.4 The CORDIC Algorithm.
12.5 Hardware Mapping of Modified CORDIC Algorithm.
13. Digital Design of Communication Systems.
13.2 Top–level Design Options.
13.3 Typical Digital Communication System.