Enter VLSI Digital Signal Processing Systems–a unique, comprehensive guide to performance optimization techniques in VLSI signal processing. Based on Keshab Parhi′s highly respected and popular graduate–level courses, this volume is destined to become the standard text and reference in the field. This text integrates VLSI architecture theory and algorithms, addresses various architectures at the implementation level, and presents several approaches to analysis, estimation, and reduction of power consumption.
Throughout this book, Dr. Parhi explains how to design high–speed, low–area, and low–power VLSI systems for a broad range of DSP applications. He covers pipelining extensively as well as numerous other techniques, from parallel processing to scaling and roundoff noise computation. Readers are shown how to apply all techniques to improve implementations of several DSP algorithms, using both ASICs and off–the–shelf programmable digital signal processors.
The book features hundreds of graphs illustrating the various DSP algorithms, examples based on digital filters and transforms clarifying key concepts, and interesting end–of–chapter exercises that help match techniques with applications. In addition, the abundance of readily available techniques makes this an extremely useful resource for designers of DSP systems in wired, wireless, or multimedia communications. The material can be easily adopted in new courses on either VLSI digital signal processing architectures or high–performance VLSI system design.
An invaluable reference and practical guide to VLSI digital signal processing.
A tremendous source of optimization techniques indispensable in modern VLSI signal processing, VLSI Digital Signal Processing Systems promises to become the standard in the field. It offers a rich training ground for students of VLSI design for digital signal processing and provides immediate access to state–of–the–art, proven techniques for designers of DSP applications–in wired, wireless, or multimedia communications.
∗ Transformations for high speed using pipelining, retiming, and parallel processing techniques
∗ Power reduction transformations for supply voltage reduction as well as for strength or capacitance reduction
∗ Area reduction using folding techniques
∗ Strategies for arithmetic implementation
∗ Synchronous, wave, and asynchronous pipelining
∗ Design of programmable DSPs.
Pipelining and Parallel Processing.
Systolic Architecture Design.
Algorithmic Strength Reduction in Filters and Transforms.
Pipelined and Parallel Recursive and Adaptive Filters.
Scaling and Roundoff Noise.
Digital Lattice Filter Structures.
Bit–Level Arithmetic Architectures.
Numerical Strength Reduction.
Synchronous, Wave, and Asynchronous Pipelines.
Programmable Digital Signal Processors.