∗ Models for interconnect as well as devices and the impact of scaling trends
∗ Modern analysis techniques, from matrix reduction and moment matching to transmission–line analysis
∗ An overview of the effects of inductance on on–chip interconnect
∗ Flexible CAD algorithms that can be generalized for different needs, from buffer insertion to wire sizing to routing topology
∗ Emphasis on realistic problem formulations, addressing key design tradeoffs such as those between area and performance
Inductance and Inductive Coupling for On–chip Interconnect.
Synthesis: Overview and Static Topology Optimization.
Global Routing Topology Synthesis.
Optimization of Multi–Source Nets.
Timing Driven Maze Routing.