ULSI Semiconductor Technology Atlas

  • ID: 2175600
  • Book
  • 666 Pages
  • John Wiley and Sons Ltd
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More than 1,100 TEM images illustrate the science of ULSI

The natural outgrowth of VLSI (Very Large Scale Integration), Ultra Large Scale Integration (ULSI) refers to semiconductor chips with more than 10 million devices per chip. Written by three renowned pioneers in their field, ULSI Semiconductor Technology Atlas uses examples and TEM (Transmission Electron Microscopy) micrographs to explain and illustrate ULSI process technologies and their associated problems.

The first book available on the subject to be illustrated using TEM images, ULSI Semiconductor Technology Atlas is logically divided into four parts:

  • Part I includes basic introductions to the ULSI process, device construction analysis, and TEM sample preparation
  • Part II focuses on key ULSI modules ion implantation and defects, dielectrics and isolation structures, silicides/salicides, and metallization
  • Part III examines integrated devices, including complete planar DRAM, stacked cell DRAM, and trench cell DRAM, as well as SRAM as examples for process integration and development
  • Part IV emphasizes special applications, including TEM in advanced failure analysis, TEM in advanced packaging development and UBM (Under Bump Metallization) studies, and high–resolution TEM in microelectronics

This innovative guide also provides engineers and managers in the microelectronics industry, as well as graduate students, with:

  • More than 1,100 TEM images to illustrate the science of ULSI
  • A historical introduction to the technology as well as coverage of the evolution of basic ULSI process problems and issues
  • Discussion of TEM in other advanced microelectronics devices and materials, such as flash memories, SOI, SiGe devices, MEMS, and CD–ROMs
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FOREWORD ix

PREFACE xi

PART I 1

1 Microelectronics and Microscopy 3

2 ULSI Process Technology 36

3 Applications of TEM for Construction Analysis 61

4 TEM Sample Preparation Techniques 90

PART II 141

5 Ion Implantation and Substrate Defects 143

6 Dielectrics and Isolation 179

7 Silicides, Polycide, and Salicide 256

8 Metallization and Interconnects 287

PART III 343

9 ULSI Devices I: DRAM Cell with Planar Capacitor 345

10 ULSI Devices II: DRAM Cell with Stacked Capacitor 365

11 ULSI Devices III: DRAM Cell with Trench Capacitor 399

12 ULSI Devices IV: SRAM 445

PART IV 475

13 TEM in Failure Analysis 477

14 Novel Devices and Materials 526

15 TEM in Under Bump Metallization (UBM) and Advanced Electronics Packaging Technologies 558

16 High–Resolution TEM in Microelectronics 609

INDEX 647

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Chih–Hang Tung
George T. T. Sheng
Chih–Yuan Lu
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