This book covers everything students and professionals need to know about CMOS reliability wearout mechanisms, from basic concepts to the tools necessary to conduct reliability tests and analyze the results. It is the first book of its kind to bring together the pertinent physics, equations, and procedures for CMOS technology reliability in one place. Divided into six relatively independent topics, the book covers:
Introduction to Reliability
Gate Dielectric Reliability
Negative Bias Temperature Instability
Hot Carrier Injection
Chapters conclude with practical appendices that provide very basic experimental procedures for readers who are conducting reliability experiments for the first time. Reliability Wearout Mechanisms in Advanced CMOS Technologies is ideal for students and new engineers who are looking to gain a working understanding of CMOS technology reliability. It is also suitable as a professional reference for experienced circuit design engineers, device design engineers, and process engineers.
1 INTRODUCTION (Alvin W. Strong).
1.1 Book Philosophy.
1.2 Lifetime and Acceleration Concepts.
1.3 Mechanism Types.
1.4 Reliability Statistics.
1.5 Chi–Square and Student t Distributions.
2 DIELECTRIC CHARACTERIZATION AND RELIABILITY METHODOLOGY (Ernest Y. Wu, Rolf–Peter Vollertsen, and Jordi Sune).
2.2 Fundamentals of Insulator Physics and Characterization.
2.3 Measurement of Dielectric Reliability.
2.4 Fundamentals of Dielectric Breakdown Statistics.
2.5 Summary and Future Trends.
3 DIELECTRIC BREAKDOWN OF GATE OXIDES: PHYSICS AND EXPERIMENTS (Ernest Y. Wu, Rolf–Peter Vollertsen, and Jordi Sune).
3.2 Physics of Degradation and Breakdown.
3.3 Physical Models for Oxide Degradation and Breakdown.
3.4 Experimental Results of Oxide Breakdown.
3.5 Post–Breakdown Phenomena.
4 NEGATIVE BIAS TEMPERATURE INSTABILITIES IN pMOSFET DEVICES (Giuseppe LaRosa).
4.2 Considerations on NBTI Stress Configurations.
4.3 Appropriate NBTI Stress Bias Dependence.
4.4 Nature of the NBTI Damage.
4.5 Impact of the NBTI Damage to Key pMOSFET Transistor Parameters.
4.6 Physical Mechanisms Contributing to the NBTI Damage.
4.7 Key Experimental Observations on the NBTI Damage.
4.8 Nit Generation by Reaction Diffusion (R D) Processes.
4.9 Hole Trapping Modeling.
4.10 NBTI Dependence on CMOS Processes.
4.11 NBTI Dependence on Area Scaling.
4.12 Overview of Key NBTI Features.
5 HOT CARRIERS (Stewart E. Rauch, III).
5.2 Hot Carriers: Physical Generation and Injection Mechanisms.
5.3 Hot Carrier Damage Mechanisms.
5.4 HC Impact to MOSFET Characteristics.
5.5 Hot Carrier Shift Models.
6 STRESS–INDUCED VOIDING (Timothy D. Sullivan).
6.2 Theory and Model.
6.3 Role of the Overlying Dielectric.
6.4 Summary of Voiding in Al Metallizations
6.5 Stress Voiding in Cu Interconnects.
6.6 Concluding Remarks.
7 ELECTROMIGRATION (Timothy D. Sullivan).
7.2 Metallization Failure.
7.4 General Approach to Electromigration Reliability.
7.5 Thermal Considerations for Electromigration.
7.6 Closing Remarks.
ERNEST Y. WU, PhD, is a Senior Technical Staff Member at Semiconductor Research and Development Center (SRDC) in the IBM System and Technology Group. He has authored or coauthored more than 100 technical or conference papers. His research interests include dielectric/device reliability and electronic physics.
ROLF–PETER VOLLERTSEN, PhD, is a Principal for Reliability Methodology at Infineon Technologies AG in Munich, Germany, where he is responsible for methods and test structures for fast Wafer Level Reliability monitoring and the implementation of fast WLR methods.
JORDI SUNE, PhD, is Professor of Electronics Engineering at the Universitat Aut¿noma de Barcelona, Spain. He is Senior Member of the IEEE and has coauthored over 150 publications on oxide reliability and electron devices. His research interests are in gate oxide physics, reliability statistics, and modeling of nanometer–scale electron devices.
GIUSEPPE LaROSA, PhD, is Project Leader of the FEOL technology reliability qualification activities for the development of advanced SOI Logic and eDRAM technologies at IBM, where he is responsible for the implementation and development of state–of–the–art NBTI stress and test methodologies.
TIMOTHY D. SULLIVAN, PhD, is Team Leader for metallization reliability at IBM′s Essex Junction facility. The author of numerous technical papers and tutorials, he holds thirteen patents with several more pending.
STEWART E. RAUCH, III, PhD, is currently a Senior Technical Staff Member at the IBM SRDC in New York, where he specializes in hot carrier and NBTI reliability of state–of–the–art CMOS devices. He is the author of numerous technical papers and tutorials and holds five patents.