Ericsson RBS6000 Digital Units ASICs Report

  • ID: 3377376
  • Report
  • Region: Global
  • 157 Pages
  • EJL Wireless Research
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Comprehensive Technology Analysis of the Digital Baseband Unit ASICs Within the Ericsson RBS6000 Base Station Platform
This report provides a comprehensive technology analysis of the digital baseband unit ASICs within the Ericsson RBS6000 base station platform. The ASICs analyzed are used in the following Ericsson digital units: DUG 10, DUG 20, DUW 10, DUW 20, DUW 30, DUL 20, DUS 31, and DUS 41. There is a total of six Ericsson baseband ASICs contained within this report.

Key features of this report:

- Wafer Fabrication ID, Silicon process node ID, Die Size and Package Analysis
- Die photograph, magnified SEM photographs, X-Ray photographs
- Die mapping of functional blocks
- Die mapping of I/Os
- Die mapping of memory structures
- Digital unit system architecture
- DSP core analysis
- Proprietary technology analysis
- Total Pages: 157
- Total Tables: 26
- Total Exhibits: 163

Ericsson and other BTS OEMs typically deploy Base Transceiver Station (BTS) systems with an average service life of 7 to 10 years. Ericsson BTS systems seem to grow more and more complex with each deployment. The LTE baseband, and specifically the digital unit (DU), perform most of the LTE standard-required functions, including baseband processing of giga-operations-per second throughput. For this reason, the DU is the most computationally intensive component of an LTE system. This report focuses on baseband processing, and specifically the ASICs used in Ericsson digital units. Currently deployed Ericsson DUs perform the baseband processing of multiple Radio Access Networks (RANs) due to the multiple standards in currently sold mobile devices. Each ASIC in an Ericsson DU is part of a software-centric Ericsson Radio System Architecture. The Ericsson RBS 6000 BTS system supports GSM/EDGE, W-CDMA/HSPA, LTE, and CDMA in a single unit.
Note: Product cover images may vary from those shown
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EXECUTIVE SUMMARY
DU Board Teardowns + ASIC RE Analysis = Invaluable Insight
Radio System Architecture History
BTS Hardware Development Compared with Software Development
Key Takeaways: Carrier Grade Cost Structure Pressure

CHAPTER 1: ERICSSON RADIO SYSTEM ARCHITECTURE
1.1 DU Boards and their ASICs
1.2 Ericsson Radio System Architecture
1.3 SOFTWARE-DEFINED RADIO
1.4 Multi-standard RAN Complexity
1.5 All RAN Ericsson Radio System (ERS)
1.6 DU ASIC CHART Overview

CHAPTER 2: DIGITAL UNIT (DU) OVERVIEW
2.1 DU System-Level Architecture Support for ASICs
2.2 DU Board-Level Architecture
2.3 DUG Subsystem
2.4 DUW Subsystem
2.5 DUL and DUS Subsystem
2.6 Common Operation and Maintenance (O&M) Features
2.7 Board/ASIC Trace and Debug Overview

CHAPTER 3: RBS DIGITAL UNIT (DU) PROCESSING
3.1 DU Analysis Scope/Process
3.2 DUL/DUS Subsystem Functionality
3.3 In-depth ASIC Analysis Process
3.4 Multi-Core Ecosystem
3.5 Atypical Trace and Debug Capabilities
3.6 DU Architectural Summary

CHAPTER 4: DU ASIC OVERVIEW
4.1 ASIC Process Nodes
4.2 ASIC Fabrication Source Analysis
4.3 Silicon Area and Function
4.4 DSP/Multi-Core Evolution

CHAPTER 5: MULTI-CORE/DSP OVERVIEW
5.1 Shift from PowerPC? to ARM Ecosystem
5.2 DSP Core Technology/Analysis
5.3 Internal DSP Cores
CHAPTER 6: DUG ASICS FOR GSM
6.1 GSM Processing Overview
6.2 Basic Structure and Architecture
6.3 I/O Analysis
6.4 DUG ASIC-2 Summary of findings

CHAPTER 7: DUW ASICS FOR W-CDMA
7.1 DUW ASICs Overview .
7.2 DUW ASIC #1 Package Analysis
7.3 DUW ASIC #1 Chip Analysis
7.4 DUW ASIC #1 Functional Analysis
7.5 DUW ASIC #2 Package Analysis
7.6 DUW ASIC #2 Chip Analysis
7.7 DUW ASIC #2 Special Structures

CHAPTER 8: DUL ASIC ANALYSIS
8.1 DUL ASIC Overview
8.2 DUL ASIC Package Analysis
8.3 DUL ASIC Chip Analysis
8.4 DUL ASIC CPU Functions
8.5 DSP Functions
8.6 Digital and Analog I/Os

CHAPTER 9: DUS ASIC ANALYSIS
9.1 DUS ASIC Overview
9.2 DUS ASIC Package Analysis
9.3 DUS ASIC Chip Analysis
9.4 Evolution from Previous ASICs
9.5 Core Processor Functions
9.6 DUS DSP Complex
9.7 Special Structures, Digital and Analog I/Os
9.8 Other DUS ASIC Proprietary Technology Analysis

CHAPTER 10: CONCLUSION

TABLES
Table 1: Ericsson BTS ASICs and Digital Unit (DU) Hardware
Table 2: Six Major Ericsson Digital Baseband Processing ASICs
Table 3: Ericsson DUG, DUW, DUL and DUS ASIC Silicon Chart
Table 4: Ericsson DUG, DUW, DUL and DUS ASIC Software Chart
Table 5: Ericsson DU DSP Block Area Chart; from DUG, DUW, DUL and DUS ASICs
Table 6: Essential RT/Embedded Communications Proprietary Technology
Table 7: Ericsson BTS ASIC and Digital Unit (DU) Hardware Components
Table 8: DUL Chip/ASIC Proprietary Technology Overview
Table 9: DUL ASIC Cortex™-R MPCore™ Memory/Register Overview
Table 10: DUL ASIC ETM™-R4/R5 Register/Memory Overview
Table 11: ETM™-R4/R5 Register/Memory Count
Table 12: ARM Cortex™-R5 Dual/MPCore™ Area Analysis
Table 13: DUL ASIC DSP Core Overview S
Table 14: DUL ASIC Digital and Analog I/Os
Table 15: DUS ASIC’s Memory Cell Types
Table 16: Comparing DUL/DUS ASIC’s ARM Cortex™-R MPCore™ Memory Blocks
Table 17: Comparing ARM Proprietary Technology in DUL/DUS ASICs
Table 18: Comparing I/O and I/O Subsystems in DUL and DUS ASICs
Table 19: Comparing ARM Proprietary Technology in DUL/DUS ASICs
Table 20: DUS ASIC DSP Area 1 and 2 Memory Blocks
Table 21: DUS ASIC DSP H Block Detail
Table 22: DUS E Block Ethernet Memory and Buffer Structures
Table 23: DUS F Block Memory Structure Analysis
Table 24: DUS ASIC G Block Detail
Table 25: DUS ASIC “K” Block
Table 26: Ericsson Radio System Architectural BTS Roadmap Requirements

EXHIBITS
Exhibit 1: Ericsson BTS System Hardware and Software Release, 2003-2016
Exhibit 2: BTS System Hardware, Software, and Service Revenue Priority
Exhibit 3: RBS 6000 Architecture showing “Digital Units” with RUs and RRUs
Exhibit 4: RBS 6000 Architecture showing Digital Units (Center Bottom)
Exhibit 5: Multi-RAT RAN according to Ericsson
Exhibit 6: GSM RAN as part of the Multi-Standard ERS
Exhibit 7: W-CDMA RAN as part of the Multi-Standard ERS
Exhibit 8: LTE RAN as part of Multi-Standard ERS
Exhibit 9: Multiple Standards in a BTS
Exhibit 10: Ericsson Radio System BTS RBS 2000/3000 and RBS 6000 Evolution
Exhibit 11: Example of DU Multi-standard Mix Mode System Support
Exhibit 12: Digital Unit – Generic Ericsson DU Block Diagram
Exhibit 13: Digital Unit Software Architectural Mapping
Exhibit 14: Mapping Basic LTE Software Functions to Hardware Proprietary Technology Cores
Exhibit 15: Digital Unit – Generic Ericsson DU Block Diagram
Exhibit 16: Baseband Digital Unit – ERS Baseband DUS XX Block Diagram
Exhibit 17: Software Layers with RT (Real-Time) Extensions
Exhibit 18: LTE Layer Multi-core SoC Software - Core and DSP
Exhibit 19: Protecting the RBS 6000 Investment
Exhibit 20: DUG 20 01 – Front Panel
Exhibit 21: DUG 20 01 – Board (Top View) with Heatsinks
Exhibit 22: DUW 20 01 – Front Panel
Exhibit 23: DUW 10, DUW 20, DUW 30, DUW 11, DUW 31, and DUW 41 versions
Exhibit 24: DUW RF/IF board and the Baseband I/O Board
Exhibit 25: DUL 20 01 – Front Panel markings, ports, and indicators
Exhibit 26: DUS 31 01/DUS 41 01 – Front Panel
Exhibit 27: Top View DUL 20 01 Board
Exhibit 28: DUS 41 01 Board Bottom View (L) and Top-View (R)
Exhibit 29: Direct to DU ASIC Equipment and Managed Objects w/LMT port
Exhibit 30: Ericsson DU Support Management System and the MOM
Exhibit 31: OSS-RC CPI Active Library Explorer (ALEX) Access
Exhibit 32: Ericsson DU ASIC Prototype Verification and Extended Trace Options
Exhibit 33: Ericsson DU ASIC Documentation Match to DUL ASIC
Exhibit 34: DUL ASIC Identified ROM and Register Structures
Exhibit 35: Debug Ports on DUL board with a Serial GigaBit Trace Interface
Exhibit 36: Processor Debug Ports on DUL board with a Serial GigaBit Trace Interface
Exhibit 37: DU ASIC Structures: CoreSight™ Embedded Trace Macrocell™
Exhibit 38: DUL Package differences between “R1A” and “R2A” ASIC Revisions
Exhibit 39: Ericsson RBS 6000 DU ASICs
Exhibit 40: Ericsson DUG, DUW, DUL, and DUS ASICs
Exhibit 41: Ericsson DUS ASIC Revisions
Exhibit 42: Software/OS Proprietary Technology: Multi-Standard LTE Macrocell Example 2012
Exhibit 43: Software/OS Boot Device Loading and Booting ASIC Devices
Exhibit 44: Software/OS Proprietary Technology: Fixed 3GPP LTE RAN Processing Requirements
Exhibit 45: Software/OS Proprietary Technology: Multi-Standard RAN
Exhibit 46: DUx Address and ASIC MO Mapping
Exhibit 47: Software/OS: Software/Hardware Driver Layering
Exhibit 48: Software/OS Proprietary Technology: Multi-Standard RAN
Exhibit 49: Illustrative BTS DU-ASIC Baseband Architecture
Exhibit 50: CEVA DSP Complex with ARM and CEVA CoreSight™
Exhibit 51: ARM Cortex™-R7 MPCore™ and CEVA XC4000 Proprietary Technology
Exhibit 52: Ericsson DUW, DUL, and DUS ASIC Processor/DSP Test Headers
Exhibit 53: Shared DUW and DUL ASIC Structures
Exhibit 54: ASIC Process Node Identification
Exhibit 55: ASIC Process Node Identification
Exhibit 56: ARM 65LPe Low Power Physical Platform
Exhibit 57: Ericsson DUW and DUL ASIC Process Technology
Exhibit 58: TSMC ASIC Fabrication Technology
Exhibit 59: Ericsson DU ASIC Processor Area Comparison
Exhibit 60: Ericsson DU ASIC DSP Block Comparisons
Exhibit 61: Ericsson DUW ASIC Logic-Based Computation Example
Exhibit 62: DUS ASIC RapidIO? Buffer
Exhibit 63: DSP Proprietary Technology Block Evolution in Ericsson DU ASICs: 2003 to 2011
Exhibit 64: SoC & ASIC Design Philosophy at Ericsson (circa 2014)
Exhibit 65: DSP Core Hardware/Software Tradeoff Example for Ericsson DUW ASIC Design
Exhibit 66: DSP PSU (Power-Scaling Unit) Proprietary Technology
Exhibit 67: Die Size Progression in the Ericsson DUG, DUW, DUL, & DUS ASICs
Exhibit 68: DUG ASICs #1 and #2
Exhibit 69: DUG ASIC #1 Markings
Exhibit 70: DUG ASIC #1 PowerPC Core
Exhibit 71: Digital Unit for GSM-DUG 20 01 Front Panel & Mechanical
Exhibit 72: DUG Diagram and Typical Multi-RAT RBS 6000 Use
Exhibit 73: DUG Block Diagram
Exhibit 74: DUG ASIC #2 Markings
Exhibit 75: Digital Unit for GSM-DUG ASIC #2 Overview
Exhibit 76: DUG ASIC #2 DSP Core
Exhibit 77: DUG ASIC #2 Dual PowerPC Core
Exhibit 78: DUG ASIC #2 Processor Core Complex w/PLL
Exhibit 79: RBS 6000 DUW Architecture featuring DUW ASICs #1 and #2
Exhibit 80: DUW Front Panel & Mechanical
Exhibit 81: DUW ASIC #1 Package Overview
Exhibit 82: DUW ASIC #1 Package X-Ray
Exhibit 83: DUW ASIC #1 Top Metal Layer with Magnified Views of the Die Logo and I/O Pads
Exhibit 84: 256-tap FIR Filter Performance examples; Logic and DSP computation
Exhibit 85: DUW ASIC #1 Si Poly Overview
Exhibit 86: DUW ASIC #1 Poly Layout SEM
Exhibit 87: DUW ASIC #1 Memory Structure Decomposition
Exhibit 88: DUW ASIC #1 Memory Structures A-F Block Decomposition ..
Exhibit 89: DUW ASIC #2 Package Overview
Exhibit 90: DUW ASIC #2 Package X-Ray
Exhibit 91: DUW ASIC #2 Die Overview and Markings
Exhibit 92: DUW ASIC #2 Main Feature Overview
Exhibit 93: DUW ASIC #2 I/O Match ULMA I/O Subsystems
Exhibit 94: DUW ASIC #2 Processing Technology
Exhibit 95: DUW ASIC #2 Analog Power Block
Exhibit 96: DUW ASIC #2 I/O Structures
Exhibit 97: DUW ASIC #2 Special Power Management Structures
Exhibit 98: DUW ASIC #2 Special Structure
Exhibit 99: DUW ASIC #2 DSP Core Structures vs. DUL ASIC DSP Core Structures
Exhibit 100: DUW ASIC #2 Memory Bit-Cell Comparison to DUL ASIC
Exhibit 101: DUL ASIC Board-Level Overview
Exhibit 102: DUL ASIC Package Revisions
Exhibit 103: DUL ASIC Package X-ray with Side-View
Exhibit 104: DUL ASIC Package Information
Exhibit 105: DUL ASIC Die Size and Top Metal Layer
Exhibit 106: DUL ASIC Die Markings
Exhibit 107: DUL ASIC Block Overview; DSP Cores, Analog, and I/O Blocks
Exhibit 108: DUL ASIC Si Structures
Exhibit 109: DUL ASIC Cortex-R MPCore™ Layout Detail
Exhibit 110: Suspected ARM CoreSight™-based ETM™
Exhibit 111: DUL ASIC Cortex™-R5 Dual/MPCore™ Analysis
Exhibit 112: ARM Cortex™-R5 Dual/MPCore™ Area Analysis
Exhibit 113: Comparison of ARM Cortex™-R5 Area to Known Cortex™-R4 Chip
Exhibit 114: DUL ASIC DSP Core 1
Exhibit 115: DUL ASIC DSP Core 2
Exhibit 116: DUL/DUS ASIC DSP Control Logic
Exhibit 117: DUL ASIC DSP Control Logic and PSU
Exhibit 118: DUL ASIC I/O Overview
Exhibit 119: Primary DUL ASIC Analog Block AN3 Overview
Exhibit 120: Primary DUL ASIC Analog Block AN2 Overview
Exhibit 121: DUL ASIC Analog Block AN1 Overview
Exhibit 122: Primary DUL Analog Blocks Overview
Exhibit 123: DUL ASIC #2 Temperature Sensor Detail
Exhibit 124: DUS ASIC Board-Level Overview
Exhibit 125: DUS ASIC Package and Die Overview
Exhibit 126: DUS ASIC OM, Plan-view, Top, with Die Markings
Exhibit 127: DUS ASIC SEM Cross Section (Seal Ring)
Exhibit 128: DUS ASIC Memory Types
Exhibit 129: DUS ASIC Overview showing ARM Cortex™-R7 MPCore™ and major blocks
Exhibit 130: DUL/DUS ASIC DSP Cores Comparison
Exhibit 131: DUS ASIC Block Overview; Areas 1 to 5, Analog, and Blocks A-X
Exhibit 132: Comparison of DUW and DUL ASICs to the DUL ASIC
Exhibit 133: Comparison of ARM Cortex™-R5 Dual Core to ARM Cortex™-R7 MPCore™
Exhibit 134: Evolution of DSP Complex in DUL and DUS ASICs
Exhibit 135: Cortex™ R-7 MPCore™ ETM™
Exhibit 136: DUS ASIC Cortex™ R-7 MPCore™ Block Overview
Exhibit 137: DUS ASIC DSP Area 1 and 2 Overview
Exhibit 138: ARM/CEVA DSP Complex in DUS ASIC
Exhibit 139: ARM/CEVA Proprietary Technology Block Diagram in the DUS ASIC
Exhibit 140: DUS ASIC “H” Block – DSP Subsystem
Exhibit 141: DUS ASIC Analog/SerDes I/O
Exhibit 142: DUS ASIC Analog Structure Overview
Exhibit 143: DUS ASIC X-Block Detail and Substructures
Exhibit 144: DUS ASIC Digital I/O Blocks Detail, 1-12
Exhibit 145: Analog block 1 (AN1) and 3 (AN3) with X-block detail
Exhibit 146: DUS ASIC 2- and 4-lane Switch Structures
Exhibit 147: DUS ASIC ROM and ARM Core Overview
Exhibit 148: DUS ASIC Area 3: ARM Core A3 Block Overview
Exhibit 149: DUS ASIC Area 4: ARM Cortex-A* A4 Block Overview
Exhibit 150: DUL ASIC I/O Overview
Exhibit 151: DUS ASIC Digital I/O Blocks Detail, 1-12
Exhibit 152: DUS ASIC B and D Block Switch Structure Overview
Exhibit 153: DUS ASIC B Block Switch Structure Detail
Exhibit 154: DUS Buffer Memory Block
Exhibit 155: DUS ASIC D Block Switch Structure Detail
Exhibit 156: DUS ASIC Analog AN2 and its E Block Controller
Exhibit 157: DUL ASIC E Block for Ethernet Control and Management
Exhibit 158: DUL ASIC F Block Overview
Exhibit 159: DUS ASIC G Block – RapidIO Subsystem
Exhibit 160: DUS ASIC G Block Structure Overview
Exhibit 161: DUS ASIC “G” Block Structure Detail
Exhibit 162: DUS ASIC “K” Block Structure Overview
Note: Product cover images may vary from those shown
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