Intel Xeon Phi Processor High Performance Programming is an all-in-one source of information for programming the Second-Generation Intel Xeon Phi product family also called Knights Landing. The authors provide detailed and timely Knights Landingspecific details, programming advice, and real-world examples. The authors distill their years of Xeon Phi programming experience coupled with insights from many expert customers - Intel Field Engineers, Application Engineers, and Technical Consulting Engineers - to create this authoritative book on the essentials of programming for Intel Xeon Phi products.
Intel® Xeon PhiT Processor High-Performance Programming is useful even before you ever program a system with an Intel Xeon Phi processor. To help ensure that your applications run at maximum efficiency, the authors emphasize key techniques for programming any modern parallel computing system whether based on Intel Xeon processors, Intel Xeon Phi processors, or other high-performance microprocessors. Applying these techniques will generally increase your program performance on any system and prepare you better for Intel Xeon Phi processors.
- A practical guide to the essentials for programming Intel Xeon Phi processors
- Definitive coverage of the Knights Landing architecture
- Presents best practices for portable, high-performance computing and a familiar and proven threads and vectors programming model
- Includes real world code examples that highlight usages of the unique aspects of this new highly parallel and high-performance computational product
- Covers use of MCDRAM, AVX-512, Intel® Omni-Path fabric, many-cores (up to 72), and many threads (4 per core)
- Covers software developer tools, libraries and programming models
- Covers using Knights Landing as a processor and a coprocessor
Section I: Knights Landing 1. Introduction 2. Knights Landing overview 3. Programming MCDRAM and Cluster modes 4. Knights Landing architecture 5. Intel Omni-Path Fabric 6. ?arch optimization advice
Section II: Parallel Programming 7. Programming overview for Knights Landing 8. Tasks and threads 9. Vectorization 10. Vectorization advisor 11. Vectorization with SDLT 12. Vectorization with AVX-512 intrinsics 13. Performance libraries 14. Profiling and timing 15. MPI 16. PGAS programming models 17. Software-defined visualization 18. Offload to Knights Landing 19. Power analysis
Section III: Pearls 20. Optimizing classical molecular dynamics in LAMMPS 21. High performance seismic simulations 22. Weather research and forecasting (WRF) 23. N-Body simulation 24. Machine learning 25. Trinity workloads 26. Quantum chromodynamics
Jim Jeffers was the primary strategic planner and one of the first full-time employees on the program that became Intel ® MIC. He served as lead SW Engineering Manager on the program and formed and launched the SW development team. As the program evolved, he became the workloads (applications) and SW performance team manager. He has some of the deepest insight into the market, architecture and programming usages of the MIC product line. He has been a developer and development manager for embedded and high performance systems for close to 30 years.
James Reinders is a senior engineer who joined Intel Corporation in 1989 and has contributed to projects including the world's first TeraFLOP supercomputer (ASCI Red), as well as compilers and architecture work for a number of Intel processors and parallel systems. James has been a driver behind the development of Intel as a major provider of software development products, and serves as their chief software evangelist. James has published numerous articles, contributed to several books and is widely interviewed on parallelism. James has managed software development groups, customer service and consulting teams, business development and marketing teams. James is sought after to keynote on parallel programming, and is the author/co-author of three books currently in print including Structured Parallel Programming, published by Morgan Kaufmann in 2012.
Avinash Sodani is the chief architect of the Knights Landing Xeon Phi Processor. He has many years of experience architecting high end processors and previously was one of the architects for the first Core(tm) processor codenamed Nehalem.