Until 2015, Apple used to integrate its application processor engine (APE) in standard Package-on-Package (PoP) packaging. Starting in 2016, with the Apple A10 APE in the Apple iPhone 7, TSMC has brought a breakthrough fan-out technology called integrated Fan-Out (inFO) packaging to the market. This is still the most innovative, powerful and cost-effective fan-out packaging technology for the APE.
For its latest flagships, the Apple iPhone 8 and tenth’s anniversary iPhone X, Apple has renewed its collaboration with TSMC by using the new generation of inFO packaging for the Apple A11 APE.
Comparing the iPhone X and the iPhone 8, Apple and its partners have integrated the two flagships’ main boards differently. In the iPhone X, the main board uses special printed circuit board (PCB) technology from AT&S to reduce its PCB footprint by about 15%. To do this, AT&S uses two stacked PCBs with components mounted on both sides and a via frame. The APE is located inside the structure, under the DRAM package, using PoP technology. This new version also features new land-side decoupling capacitor (LSC) technology.
The Apple A11 is a wafer-level package using the new generation of TSMC’s packaging technology. It uses copper pillars, called Through inFO Vias (TiVs), to replace the well-known Through Molded Via (TMV) technology. Apple still outperforms standard PoP technology thanks to the inFO packaging and its innovations, which include copper pillars, redistribution layers and silicon high density capacitor integration.
This report analyzes the complete package, from the DRAM memory to the LSC developed by TSMC. The report includes a comprehensive cost analysis and price estimation of the device based on detailed description of the packaging. It also features a detailed technology comparison with standard PoP and Shinko’s MCeP PoP packaging.
2. Apple Company Profile and inFO Technology
3. Apple iPhone 8 and iPhone X Teardown
4. Physical Analysis
Physical Analysis Methodology
A11 Packaging Analysis
Package view and dimensions: X-ray, RDL deprocessing, RDL line/space width
Package opening: DRAM memories, APE die
Board and package cross-section: via frame, main board PCB, TiV, adhesives, RDLs
Land-Side Decoupling Capacitor
Die view and dimensions
Die overview and delayering
5. Manufacturing Process Flow
Packaging Fabrication Unit
inFO Package Process Flow
Deep Trench Capacitor (DTC) Chip Fabrication Unit
DTC Process Flow
6. Cost Analysis
Summary of the Cost Analysis
Supply Chain Description
A11 Die Cost Analysis
DTC Die Cost Analysis
inFO Package Cost Analysis
inFO wafer front-end cost
inFO cost per process step
Final Test Cost