In automotive applications, radio-frequency (RF) complementary metal-oxide-semiconductor (CMOS) is the next technology generation for radar integrated circuits (ICs). Among its advantages, low power consumption is the main benefit. This could be attractive to other domains, like the Internet of Things. Indeed, the small form factor, along with the low power consumption, could be suitable for applications like garbage monitoring or parking regulation. Acconeer, a Swedish company, has developed and started to produce a chip that could be used in these applications, the A111. In addition to RFCMOS, the company has chosen an Antenna-in-package (AiP) technology in order to provide the smallest form factor.
This makes the A111 the most integrated radar chipset currently available on the market. It features two channels, one receiver and one transmitter, along with a controller, power management and a timing block, all on the same die. This chipset is extremely compact compared to other products on the market.
With this component Acconeer mainly targets industrial applications using pulsed coherent radar (PCR) technology. The system is designed for high-precision measurement and ultra-low power. The baseband, the RF Front-End and the antenna are delivered in a single package. The System-on-Chip for the signal processing is placed in flip-chip configuration under a printed circuit board featuring the antennas and the solder balls. By having the AiP and the PCR technology in the same device, Acconeer produces a low cost, low power, millimeter-level accuracy and high update frequency device.
This report reviews the A111, including a complete die analysis, cost analysis, and price estimate for the chips. Also included is a physical and technical comparison with Texas Instruments’ IWR6843AoP.
2. Acconeer – Company Profile
3. Physical Analysis
- Physical Analysis – Methodology
- Package Assembly
- View and dimensions
- Package overview and cross-section
- Package opening
- View, dimensions, and markings
- Die overview
- Die process
- Cross-section and process characteristics
4. Physical Comparison with IWR6843AoP
5. Manufacturing Process Flow
- Die Process and Wafer Fabrication Unit
- Packaging Process and Fabrication Unit
6. Cost Analysis
- Cost Analysis Overview
- Main Steps Used in the Economic Analysis
- Yield Hypotheses
- Die Cost
- Front-end (FE) cost
- Wafer and die cost
- Packaging Assembly Cost
- Component Cost
7. Estimated Price Analysis