As designs increase in complexity, so has the value of verification engineers within the hardware design team. In fact, the need for skilled verification engineers has grown dramatically--functional verification now consumes between 40 and 70% of a project's labor, and about half its cost. Currently there are very few books on verification for engineers, and none that cover the subject as comprehensively as this text.
A key strength of this book is that it describes the entire verification cycle and details each stage. The organization of the book follows the cycle, demonstrating how functional verification engages all aspects of the overall design effort and how individual cycle stages relate to the larger design process. Throughout the text, the authors leverage their 35 plus years experience in functional verification, providing examples and case studies, and focusing on the skills, methods, and tools needed to complete each verification task.
- Comprehensive overview of the complete verification cycle- Combines industry experience with a strong emphasis on functional verification fundamentals- Includes real-world case studies
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Part I: Introduction to Verification
Chapter 1: Verification in the Chip Design Process
Chapter 2: Verification Flow
Chapter 3: Fundamentals of Simulation Based Verification
Chapter 4: The Verification Plan
Part II: Simulation-Based Verification
Chapter 5: HDLs and Simulation Engines
Chapter 6: Creating Environments
Chapter 7: Strategies for Simulation-based Stimulus Generation
Chapter 8: Strategies for Results Checking in Chapter 9: Pervasive Function Verification
Chapter 10: Re-Use Strategies and System Simulation
Part III: Formal Verification
Chapter 11 Introduction to Formal Verification
Chapter 12 Using Formal Verification
Part IV: Comprehensive Verification
Chapter 13: Completing the Verification Cycle
Chapter 14: Advanced Verification Techniques
Part V: Case Studies
Chapter 15: Case Studies