Critical Materials Report Precursors-Dielectric

1.1 Highlight Material Segment Business Trends (M&A, plant closures, new suppliers, etc.)
1.2 Highlight Material Segment Technology Trends
1.3 5-Year Material Segment Forecast
1.4 EHS/Logistics
1.5 Concludes with analyst assessment of the covered materials market

2.1 Scope
2.2 Purpose
2.3 Methodology

3.1 Worldwide Economy
3.2 Electronic Goods Market
3.3 IT / Data Systems
3.4 Smart Phone Market
3.5 PC Computers
3.6 Automotive
3.7 Semiconductor Device Outlook
3.8 Equipment Spending and Fab and Capital Investments
3.9 MEMS & Legacy Devices
3.10 Wafer Start Forecast
3.11 Overall China Market News and Trends
3.12 Semiconductor Market Overview Summary

4.1 Technical drivers/material change & transitions
4.1.1 Material trends for the leading-edge
4.1.2 Multi-patterning & EUV Lithography
4.2 Interconnect Trends
4.3 Logic Transistor Evolution
4.3.1 5 nm and beyond
4.4 Extending FinFET to Horizonal Nanowires GAA FETs
4.5 Realizing vertical Logic - Going vertical (2.5/3D)
4.6 Memory Evolution & Future Trends
4.6.1 DRAM
4.6.2 2D to 3D NAND transition
4.6.3 Trends/impact/status of legacy materials
4.7 Comment on Regional trends/drivers
4.8 EHS and, if possible, Logistics issues*
4.9 Changes in standard packaging/valve types

5.1 M&A Activity
5.1.1 Linde-Praxair
5.1.2 DowDuPont
5.1.3 Versum Materials takeover deal by Merck KGaA
5.1.4 MPD Chemicals acquires Norquay Technology
5.2 New plants/New entrants
5.3 Identify recently closed plants or ”to be” closed plants
5.4 New entrants
5.4.1 Adekas´new liquid Yttrium precursor
5.4.2 Strem Chemicals’ offers new La-FMD ALD precursor for future leading-edge logic and memory products
5.4.3 RASIRC : Effective Silicon and Metal Nitride Deposition at Reduced Temperature using Brute Hydrazine
5.5 Si-Precursors
5.5.1 Precursor IP filing
5.5.2 Dielectric precursor IP
5.5.3 ALD IP filing and global distribution of IP
5.5.4 Dielectrics and High-? IP trends
5.5.5 Cobalt CVD/ALD deposition IP trends
5.6 Suppliers or parts/product lines that are at risk of discontinuance or capacity reduction
5.7 Materials Market Size & Forecast
5.7.1 Advanced dielectric ALD/CVD/SOD precursors
5.7.2 Market Shares and Regional Shares
5.7.3 Analyst Assessment and outlook for raw materials supply-chain issues

• Appendix 1: Copper Interconnect History & Status
• Appendix 2: Fundamentals of thin film deposition by CVD, ALD, and SOD, and ASD and ALE

6.1 Chemical Vapor Deposition - CVD
6.2 Atomic Layer Deposition - ALD
6.3 Spin-on Dielectrics (SOD)

• Appendix 3: Acronyms

Figure 1 Wafer Starts by Technology Node and Device Type - 2/2019 modified to show the high growth nodes concerning ALD, CVD, and SOD
Figure 2 : Metal and High-? Precursor Market Shares by Precursor Type Estimates
Figure 3 Dielectric Precursor Market Shares by Precursor Type Estimates for 2019 & 2024.
Figure 4 2018 Global Economy and the Electronics Supply Chain
Figure 5 Worldwide Semiconductor Sales
Figure 6 Global Purchasing Managers Index
Figure 7 Global Electronics Production Annual Growth
Figure 8 Global Electronics Production Annual Growth
Figure 9 Automotive Electronic Content Growth
Figure 10 Automotive Semiconductor Market Growth
Figure 11 2019 Semiconductor Revenue Growth Forecasts
Figure 12 2019 Semiconductor Market Size by Device Segment
Figure 13 Semiconductor Device Unit Growth
Figure 14 200 mm Fab Capacity Outlook to 2022
Figure 15 Wafer Starts by Technology Node and Device Type - 2/2019
Figure 16 China IC Production Share and Consumption Trends
Figure 18 IC Technology Roadmap Evolutions and Revolutions
Figure 19 Process and materials changes required to shrinking logic and memory devices
Figure 20 Double patterning by increases density so called LELE for “Litho-Etch-Litho-Etch
Figure 21 Self-aligned quadruple patterning (SAQP)
Figure 22 Hardmask and Relationship to Pattern Collapse
Figure 23 Dimensional scaling under pressure
Figure 24 EPE is the difference between the intended and the printed features of an IC layout. Shrinking dimensions exacerbate EPE issues
Figure 33 The evolution of High-? / Metal Gate Transistors, from planar 45 nm to the 14 nm node
Figure 34 Comparison of CMOS Transistor used today. (A) Planar, (B) FD-SOI and (C) FinFET
Figure 35 Possible uses for dielectrics in state of the art 10 nm FinFET Technology
Figure 36 Logic Process nodes compared
Figure 37 Logic Technology Industry Roadmap (TechInsight, January 2018)
Figure 38 After the introduction at 22 nm by Intel a taller fin height and narrower fin width leads to more vertical profile in 14 nm and 10 nm
Figure 39 Leading-edge Logic Wafer Starts, historical and forecasted
Figure 40 Air Spacers Used Between Gates and Contacts
Figure 41 A Gate-all-around FET that could come into play at 5 or 3 nm
Figure 42 Imec CMOS Roadmap
Figure 43 Imec has achieved the CMOS integration of vertically stacked gate-all-around (GAA) silicon nanowire MOSFETs
Figure 44 Three principal Cross-section simulation of (a) finFET, (b) nanowire, and (c) nanosheet
Figure 45 TEM cross section of 5nm-node GAA-FETs by IBM, Samsung and GlobalFoundries
Figure 46 Leti roadmap for introducing monolithic 3D Logic scaling at 5 nm
Figure 47 Stacking FinFETs on FinFETs
Figure 48 DRAM nodes by the top 3 companies, Samsung, SK Hynix and Micron (Elpida, Nanya) compared with Winbond and the Chinese DRAM manufactures
Figure 49 The implications of the transition to 3DNAND, less dielectrics for multiple patterning but more for the multilayer stack as well as etch hardmasks (Applied Materials)
Figure 50 Transition from 2D to 3DNAND
Figure 51 NAND Technology Roadmap
Figure 52 Wafer forecast for XPoint memory
Figure 53 Ferroelectric hafnium oxide by ALD can be integrated in 3D capacitors (FRAM) in BEOL as well as in a FEOL HKMG stack (FeFETs).
Figure 54 An overview of emerging memory technologies that has been announced by the major players.
Figure 55 Introduction of High-? in high volume production
Figure 56 Adeka yttrium precursor Y-5000
Figure 57 La-FMD is a promising metal-amidinate ALD precursors for lanthanum (La) based ALD thin-films which are potentially strong candidates for high-? gate dielectric in the next generation of CMOS technology
Figure 58 TiNx grown with Brute Hydrazine at 300°C gives comparable resistivity to TiNx grown with NH3 at 400°C
Figure 64 Air Liquide New SAM for multiple patterning
Figure 65 The relative age distribution of segmented dielectric precursors filed by OEMs, chemical companies, fabricators and research organizations over the last two decades.
Figure 66 Distribution of dielectric precursor IP by OEMs, IDM/Foundries and Chemical Suppliers
Figure 67 Filed IP in the field of Atomic Layer deposition
Figure 68 Global Filed IP in the field of Atomic Layer deposition
Figure 69 PEALD publications for dielectrics
Figure 70 Dielectric and High-? IP Applications segmented by deposition method
Figure 71 High-? IP Applications segmented by metal oxide type
Figure 72 Cobalt IP-filing
Figure 73 Cobalt CVD/ALD process and hardware IP
Figure 74 IP Applications for Cobalt chemical compounds 2011 to 2018
Figure 77 Dielectric Precursor Market Shares by Precursor Type Estimates for 2019 & 2024.
Figure 78 Dielectric Precursor Market Forecast Estimates 2015 to 2024 (CAGR of 13%)
Figure 82 2018 WW Market Shares Dielectric Precursor Suppliers Estimate
Figure 83 2018 Regional Market Shares - Dielectric Precursor Shipments 2018-2019
Figure 91 : The copper damascene and dual damascene process for copper interconnects
Figure 92 : The fundamental differences between continuous, pulsed and atomic layer processing.
Figure 93: CVD vs. Spin on Deposition Processes

Table 1 Global GDP and Semiconductor Revenues
Table 2 IMF World Economic Outlook
Table 3 World Bank GDP Forecast
Table 4 Worldwide IT Spending Forecast (Billions of U.S. Dollars)
Table 5 Smartphone Vendor Shipments (Millions of Units)
Table 6 VLSI Research Semiconductor Revenue by Segment
Table 7 2019 Semiconductor Equipment Outlook
Table 8 Top IDM and Foundry Capex Spenders
Table 9 2019 Investment Plans for Selected Device Companies
Table 17: OEM Tool Sets for Sub-5 nm Logic devices
Table 18 : Critical thermal budget steps summary in a planar FDSOI integration and 3D CoolCube process for top FET in 3DVLSI.
Table 19 Assessment of China need for advanced ALD/CVD precursors
Table 20 Overview of ALD OEMs supplying 200 mm tools
Table 21 Market Segmentation Categories