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The Global Co-Packaged Optics Market 2026-2036

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    Report

  • 320 Pages
  • November 2025
  • Region: Global
  • Future Markets, Inc
  • ID: 6190418

The global co-packaged optics (CPO) market stands at an inflection point, poised to fundamentally transform data center interconnect architecture over the coming decade. Driven primarily by the explosive growth of artificial intelligence workloads, particularly large language models and generative AI, CPO technology addresses critical bottlenecks in bandwidth, power consumption, and latency that conventional pluggable optical modules can no longer overcome.

Co-packaged optics integrates optical transceivers directly with switch ASICs or processors within the same package, dramatically shortening the electrical path between computing silicon and optical conversion. This architectural shift reduces power consumption from approximately 15 picojoules per bit with pluggable modules to around 5 picojoules per bit, with a projected path to below 1 picojoule per bit. The technology also enables significantly higher bandwidth density at the package edge, essential for next-generation switches operating at 51.2 terabits per second and beyond.

The market divides into two primary application segments: scale-out and scale-up networks. Scale-out applications encompass traditional data center switching fabrics using Ethernet or InfiniBand protocols, connecting racks and clusters across the facility. Scale-up applications target GPU-to-GPU and accelerator interconnects within AI training clusters, replacing copper-based solutions like NVIDIA's NVLink with optical alternatives that offer superior reach, bandwidth, and power efficiency. Initial CPO deployments are expected to target scale-up AI networks before expanding to broader scale-out infrastructure.

NVIDIA's announcement of Spectrum-X and Quantum-X silicon photonics switches at GTC 2025 marked a watershed moment for the industry, signaling that the dominant AI infrastructure provider is fully committed to CPO technology. These switches leverage TSMC's System on Integrated Chips (SoIC) technology with 3D hybrid bonding to achieve unprecedented integration density. Broadcom, the leading switch ASIC supplier, has pursued a complementary strategy with its Bailly CPO platform, emphasizing an open ecosystem approach that works with multiple packaging and photonics partners.

The CPO supply chain represents one of the semiconductor industry's most complex ecosystems, spanning photonic integrated circuit design, laser sources, electronic interface circuits, advanced packaging, optical alignment, and system integration. TSMC has emerged as a central player, providing both leading-edge logic processes and advanced packaging platforms including CoWoS and COUPE that enable tight integration of photonic and electronic chiplets. Critical bottlenecks remain in optical assembly and testing, where sub-micron alignment tolerances and specialized equipment create manufacturing challenges that the industry is actively working to resolve.

Key technology decisions facing the industry include the choice between 2.5D and 3D integration approaches, external versus integrated laser sources, and edge coupling versus grating coupling for fiber attachment. Most leading implementations have converged on external laser source architectures that keep temperature-sensitive lasers separate from heat-generating ASICs, improving reliability and enabling redundancy. Hybrid bonding technology is increasingly favored for achieving the interconnect density required for next-generation optical engines.

Hyperscale cloud providers including AWS, Microsoft Azure, Google, and Meta represent the primary demand drivers, with their massive AI infrastructure investments creating urgent requirements for CPO solutions. These companies collectively invest tens of billions of dollars annually in data center infrastructure and are actively evaluating or developing CPO technology for deployment beginning in 2026-2027.

The competitive landscape features established semiconductor giants alongside well-funded startups. Companies like Ayar Labs, Lightmatter, and Celestial AI are pioneering novel architectures including 3D photonic interposers and photonic fabric technologies that may reshape the market. Meanwhile, traditional optical component suppliers including Lumentum, Coherent, and Marvell are adapting their portfolios for CPO applications. As AI model sizes continue growing exponentially and data center power constraints tighten, CPO technology offers a compelling solution to interconnect challenges that will only intensify. The technology's ability to deliver higher bandwidth at lower power positions it as essential infrastructure for the AI era.

The Global Co-Packaged Optics Market 2026-2036 delivers comprehensive analysis of the rapidly emerging CPO industry, examining how this transformative technology is reshaping data centre interconnect architecture to meet the unprecedented bandwidth demands of artificial intelligence and machine learning workloads. As hyperscale operators and AI infrastructure providers confront critical limitations in power consumption, latency, and bandwidth density with conventional pluggable optical modules, co-packaged optics has emerged as the definitive next-generation solution, integrating optical transceivers directly with switch ASICs and accelerators to achieve dramatic improvements in performance and efficiency.

This authoritative report provides semiconductor industry professionals, investors, data centre operators, and technology strategists with detailed market forecasts projecting CPO growth from nascent commercial deployments through mass adoption, with granular segmentation by application (scale-out networking and scale-up AI interconnects), integration technology (2D, 2.5D, and 3D packaging), and end-use sector. The research examines the complete CPO value chain, from photonic integrated circuit design and laser sources through advanced semiconductor packaging and system integration, identifying critical bottlenecks, emerging solutions, and strategic opportunities across each segment.

Drawing on extensive primary research including interviews with industry leaders across the CPO ecosystem, the report delivers actionable intelligence on technology roadmaps from dominant players including NVIDIA and Broadcom, evaluates competing packaging approaches from leading OSATs and foundries, and assesses the readiness of hyperscale customers to deploy CPO at scale. Detailed company profiles provide strategic analysis of 55 organisations actively shaping the CPO landscape, while comprehensive benchmarking enables direct comparison of competing technologies, products, and ecosystem strategies.

Report contents include:

  • Market Analysis and Forecasts
    • Ten-year market forecasts (2026-2036) for total CPO market size and revenue
    • Optical I/O for AI interconnect unit shipment and revenue projections
    • CPO network switch unit shipment and market size forecasts
    • Server board, CPU, and GPU/accelerator demand forecasts driving CPO adoption
    • Segmentation by EIC/PIC integration technology and packaging approach
    • Regional analysis and adoption timeline projections
  • Technology Analysis
    • Comprehensive examination of photonic integrated circuit (PIC) architectures and silicon photonics
    • Optical engine design principles, components, and performance benchmarks
    • Detailed analysis of 2D, 2.5D, and 3D EIC/PIC integration approaches
    • Through-silicon via (TSV), fan-out, glass-based, and hybrid bonding packaging technologies
    • Fiber array unit (FAU) alignment challenges and solutions
    • Laser integration methods including external laser source architectures
    • Universal Chiplet Interconnect Express (UCIe) implications for CPO
  • Application Analysis
    • Scale-out network switch CPO for Ethernet and InfiniBand fabrics
    • Scale-up optical I/O for GPU-to-GPU and AI accelerator interconnects
    • Comparison of CPO, pluggable optics, and copper interconnect approaches
    • Power efficiency analysis: CPO vs. pluggable vs. copper (pJ/bit benchmarks)
    • Latency performance comparisons across interconnect technologies
    • Migration roadmaps from copper to optical in AI infrastructure
  • Industry and Supply Chain Intelligence
    • Complete CPO industrial ecosystem mapping across ten value chain segments
    • PIC design, ASIC/xPU, laser sources, wafer/substrate suppliers analysis
    • EIC, SerDes, PHY, and retimer supplier landscape
    • Connector and fiber infrastructure provider assessment
    • Foundry capabilities for silicon photonics and advanced packaging
    • OSAT packaging, assembly, and test service provider evaluation
    • System integrator and ODM/OEM positioning
    • Hyperscaler end customer requirements and adoption timelines
    • Ecosystem interdependencies and strategic implications
  • Competitive Intelligence
    • NVIDIA vs. Broadcom strategic comparison in AI infrastructure and CPO
    • Product benchmarking: Spectrum-X, Quantum-X, Bailly platform specifications
    • Divergent ecosystem strategies and partnership analysis
    • Start-up innovation landscape: Ayar Labs, Lightmatter, Celestial AI, and others
    • Foundry platform comparison: TSMC COUPE/iOIS, GlobalFoundries Fotonix
  • Challenges and Solutions
    • SerDes bottlenecks in high-bandwidth systems and mitigation approaches
    • Thermal management challenges in CPO module design
    • Optical alignment precision requirements and manufacturing solutions
    • Reliability considerations: redundancy, monitoring, and self-correction
    • Testing strategies for wafer-level and package-level optical validation
    • Standardisation efforts and interoperability considerations

Table of Contents

1 EXECUTIVE SUMMARY
1.1 Report Overview and Key Findings
1.2 Market Definition and Scope
1.3 Key Market Drivers and Restraints
1.4 Modern High-Performance AI Data Centre Architecture
1.5 Switches: Key Components in Modern Data Centres
1.6 Advancements in Switch IC Bandwidth and the Need for CPO Technology
1.7 Overview of Key Challenges in Data Centre Architectures
1.8 Key Trend of Optical Transceivers in High-End Data Centres
1.9 Design Decisions: CPO vs. Pluggables Comparison
1.10 What is an Optical Engine (OE)?
1.11 Heterogeneous Integration and Co-Packaged Optics
1.15 Overview of Interconnection Techniques in Semiconductor Packaging
1.16 Key CPO Applications: Network Switch and Computing Optical I/O
1.17 EIC/PIC Integration by Advanced Interconnect Techniques
1.18 2D to 3D EIC/PIC Integration Options
1.19 Benchmark of Different Packaging Technologies for EIC/PIC
1.20 Examples of Packaging a 3D Optical Engine with an IC
1.21 Three Types of CPO XPU/Switch ASIC Packaging Structures
1.22 Challenges and Future Potential of CPO Technology
1.23 NVIDIA vs. Broadcom: Strategic Comparison in AI Infrastructure and CPO
1.23.1 CPO Product Benchmark: NVIDIA vs. Broadcom
1.23.2 NVIDIA and Broadcom: Divergent CPO Ecosystems
1.24 Current AI System Architecture
1.25 Future AI Architecture
1.26 Market Forecast
1.26.1 Server Boards, CPUs, and GPUs/Accelerators
1.26.2 Optical I/O for AI Interconnect CPO Forecast (Units Shipped)
1.26.3 Optical I/O for AI Interconnect CPO Forecast (Revenue/Market Size)
1.26.4 CPO Network Switches for AI Accelerators Forecast (Units Shipped)
1.26.5 CPO Network Switches for AI Accelerators Forecast (Market Size and Revenue)
1.26.6 Total CPO Market Overview
1.26.7 Total CPO by Different EIC/PIC Integration Technology (Unit Shipments)
1.26.8 System Integration of Network Switches by Packaging Technologies
1.26.9 System Integration of Optical I/O Forecast by Packaging Technologies
1.27 Co-packaged optics (CPO) industrial ecosystem
1.27.1 PIC Design Segment
1.27.2 ASIC and xPU Design Segment
1.27.3 Laser Sources Segment
1.27.4 SOI Wafer and Epi-Wafer Segment
1.27.5 EIC, Retimers, SerDes, and PHY Segment
1.27.6 Connectors and Fibers Segment
1.27.7 Foundries Segment
1.27.8 Packaging, Assembling, and Testing Segment
1.27.9 System and Equipment Segment
1.27.10 End Customers (Hyperscalers) Segment
1.27.11 Ecosystem Interdependencies and Strategic Implications

2 CHALLENGES AND SOLUTIONS FOR FUTURE AI SYSTEMS
2.1 The Rise and Challenges of Large Language Models (LLMs)
2.1.1 The Explosive Growth of AI and Generative AI
2.1.2 Modern High-Performance AI Data Centre Requirements
2.1.3 NVIDIA's State-of-the-Art AI Systems
2.1.4 Switches: Key Components in Modern Data Centres
2.2 Scale-Up, Scale-Out, and Scale-Across Networks
2.2.1 Scale-Up Networks: GPU-to-GPU Interconnects
2.2.2 Scale-Out Networks: Rack-to-Rack Communications
2.2.3 Scale-Up, Scale-Out, and Scale-Across Comparison
2.3 Challenges in Network Switch Interconnects for High-End Data Centres
2.3.1 Roadmap of Interconnect Technology for Network Switches in High-End Data Centres
2.3.2 SerDes Bottleneck in High-Bandwidth Systems
2.3.3 Solutions to SerDes Bottlenecks in High-Bandwidth Systems
2.3.4 Pluggable Optics: Current Bottlenecks and Limitations
2.3.5 On-Board Optics (OBO)
2.3.6 Co-Packaged Optics (CPO)
2.3.7 Transmission Losses in Pluggable Optical Transceiver Connections
2.3.8 Pluggable Optics vs. CPO
2.3.9 Design Decisions for CPO Compared to Pluggables
2.3.10 Advancements in Switch IC Bandwidth and the Need for CPO Technology
2.3.11 L2 Frontside Network Architecture Diagram: CPO vs. Non-CPO
2.4 Challenges in Compute Switch Interconnects (Optical I/O) for High-End Data Centres
2.4.1 Number of Copper Wires in Current AI System Interconnects
2.4.2 Limitations of Current Copper Systems in AI
2.4.3 NVIDIA's Connectivity Choices: Copper vs. Optical for High-Bandwidth Systems
2.4.4 Copper vs. Optical for High-Bandwidth Systems: Benchmark
2.4.5 Migration from Copper to Optical Interconnects for High-End AI Systems
2.4.6 Current AI System Architecture
2.4.7 L1 Backside Compute Architecture with Copper Systems
2.4.8 L1 Backside Compute Architecture with Optical Interconnect: Co-Packaged Optics (CPO)
2.4.9 Opportunities for Swapping Copper to Optical
2.5 Future AI Systems in High-End Data Centres
2.5.1 Power Efficiency Comparison: CPO vs. Pluggable Optics vs. Copper Interconnects
2.5.2 Latency of 60cm Data Transmission Technology Benchmark
2.5.3 Future AI Architecture (Short to Mid-Term)
2.5.4 Future AI Architecture (Long-Term)

3 INTRODUCTION TO CO-PACKAGED OPTICS (CPO)
3.1 Photonic Integrated Circuits (PICs) Key Concepts
3.1.1 What are Photonic Integrated Circuits (PICs)?
3.1.2 PICs vs. Silicon Photonics: What are the Differences?
3.1.3 PIC Architecture
3.1.4 Advantages and Challenges of PICs
3.2 Optical Engine (OE)
3.2.1 What is an Optical Engine?
3.2.2 How an Optical Engine Works
3.2.3 Optical Power Supplies
3.3 Co-Packaged Optics
3.3.1 Three Key Concepts in Co-Packaged Optics (CPO)
3.3.2 Key Technology Building Blocks for CPO
3.3.3 Benefits of CPO: Latency Reduction
3.3.4 Benefits of CPO: Power Consumption Reduction
3.3.5 Benefits of CPO: Data Rate Improvements
3.3.6 Overview of Value Proposition of CPO
3.3.7 Future Challenges in CPO

4 PACKAGING FOR CO-PACKAGED OPTICS (CPO)
4.1 Introduction to CPO Packaging
4.1.1 Key Components to be Packaged in an Optical Transceiver
4.1.2 Heterogeneous Integration and Co-Packaged Photonics
4.1.3 CPO for Network Switch: Packaging Concept
4.1.4 1.6 Tbps Co-Packaged Optics for Network Switch
4.1.5 CPO as Optical I/O for XPUs: Packaging Concept
4.1.6 CPO Integration for Compute Silicon
4.1.7 Overview of CPO Packaging Technologies
4.2 Overview and Development Roadmap of 2.5D and 3D Advanced Semiconductor Packaging Technologies
4.2.1 Evolution Roadmap of Semiconductor Packaging
4.2.2 Semiconductor Packaging: Overview of Technology
4.2.3 Key Metrics for Advanced Semiconductor Packaging Performance
4.2.4 Overview of Interconnection Techniques in Semiconductor Packaging
4.2.5 Overview of 2.5D Packaging Structure
4.3 2.5D Silicon-Based Packaging Technologies
4.3.1 2.5D Packaging Involving Silicon as Interconnect
4.3.2 Through-Silicon Via (TSV): Current State and Future
4.3.3 Development Trends for 2.5D Silicon-Based Packaging
4.3.4 Silicon Interposer vs. Silicon Bridge Benchmark
4.4 2.5D Organic-Based Packaging Technologies
4.4.1 2.5D Packaging: High-Density Fan-Out (FO) Packaging
4.4.2 Redistribution Layer (RDL)
4.4.3 Electronic Interconnects: SiO2 vs. Organic Dielectric
4.4.4 Panel Level Fab-Out
4.4.5 Wafer Level Fan-Out
4.4.6 Wafer-Level Fan-Out vs. Panel-Level Fan-Out
4.4.7 Key Trends in Fan-Out Packaging
4.4.8 Challenges in Future Fan-Out Processes
4.5 2.5D Glass-Based Packaging Technologies
4.5.1 Roles of Glass in Semiconductor Packaging
4.5.2 Glass Core as Interposer for Advanced Semiconductor Packaging
4.5.3 Overcoming Limitations of Silicon Interposers with Glass
4.5.4 Glass vs. Molding Compound
4.5.5 Glass Core (Interposer) Package: Process Flow
4.5.6 Challenges of Glass Packaging
4.6 3D Advanced Semiconductor Packaging Technologies
4.6.1 Evolution of Bumping Technologies
4.6.2 Challenges in Scaling Bumps
4.6.3 Micro-Bump for Advanced Semiconductor Packaging
4.6.4 Bumpless Cu-Cu Hybrid Bonding
4.6.5 Three Ways of Cu-Cu Hybrid Bonding: Benchmark
4.6.6 Challenges in Cu-Cu Hybrid Bonding Manufacturing Process
4.7 CPO Packaging: EIC and PIC Integration
4.7.1 EIC/PIC Integration by Conventional Interconnect Techniques
4.7.2 EIC/PIC Integration by Emerging Interconnect Techniques
4.7.3 2D to 3D EIC/PIC Integration Options
4.7.4 Benchmark Table of Different Packaging Technologies for EIC/PIC
4.7.5 Pros and Cons of 2D Integration of EIC/PIC
4.7.6 Pros and Cons of 2.5D Integration of EIC/PIC
4.7.7 Pros and Cons of 3D Hybrid Integration of EIC/PIC
4.7.8 Pros and Cons of 3D Monolithic Integration of EIC/PIC
4.8 TSV for EIC/PIC Integration
4.8.1 TSV for EIC/PIC Integration in CPO
4.8.2 Benefits of TSV for PIC/EIC Integration
4.8.3 Key TSV Fabrication Steps and Challenges in CPO
4.8.4 Packaging Options for Silicon Photonics
4.8.5 Pros and Cons of 2.5D Si Interposer for EIC/PIC Integration
4.9 Fan-Out for EIC/PIC Integration
4.9.1 ASE's Proposed Fan-Out Solution for CPO Packaging
4.9.2 FOPOP from ASE: Process
4.9.3 Detailed Analysis of FOPOP vs. Wire Bond Packaging for CPO
4.9.4 Optical Packaging Process Considerations for Silicon Photonics - ASE
4.9.5 Process Flow of Integrating PIC and EIC in a FOEB Structure
4.9.6 Process Challenges in Packaging Optical Engines
4.9.7 Challenges of Using Fan-Out for EIC/PIC Integration
4.10 Glass-Based CPO Packaging Technologies
4.10.1 Glass-Based Co-Packaged Optics
4.10.2 Glass-Based Co-Packaged Optics: Packaging Structure
4.10.3 Glass-Based Co-Packaged Optics: Process Development
4.11 Hybrid Bonding for EIC/PIC Integration
4.11.1 TSMC: Integrated HPC Technology Platform for AI
4.11.2 iOIS: Integrated Optical Interconnection System from TSMC
4.11.3 Combining EIC and PIC with 3D SoIC Bond
4.11.4 Roadmap of Bond Pitch Scaling
4.12 System Integration of Optical Engine and ASIC/XPU
4.12.1 Co-Packaging vs. Co-Packaged Optics (CPO)
4.12.2 Three Types of CPO XPU/Switch ASIC Packaging Structures
4.13 Future 3D-CPO Structure
4.13.1 NVIDIA's 3D Integration of SoC, HBM, EIC, and PIC on Co-Packaged Substrates
4.13.2 Process in Fabrication of the 3D Heterogeneous Integration of EIC and PIC on a Glass Interposer
4.13.3 Challenges and Future Potential of CPO Technology
4.14 Optical Alignment and Laser Integration
4.14.1 How CPO is Built and the Bottleneck
4.14.2 Interface Between Coupler and FAU
4.14.3 Challenges in High-Density Optical I/O for Silicon Photonics
4.15 Fiber Array Unit (FAU)
4.15.1 Optical Alignment Challenges and Solutions
4.15.2 Two Alignment Approaches
4.15.3 Key Technical Challenges
4.15.4 Fiber Array Unit
4.15.5 Fiber Attach Methods
4.15.6 Key Players in FAU for CPO
4.15.7 Benchmark of Optical Fiber Alignment Structure Variations
4.15.8 Suppliers of Other Optical Components in CPO
4.16 Laser Integration
4.16.1 On-Chip Light Source Integration Methods
4.16.2 External Lasers for CPO
4.16.3 Laser Attach Technology Benchmark
4.16.4 Benchmark of Different Laser Integration Technologies

5 GLOBAL MARKET TRENDS IN DATACOM
5.1 Application Trends
5.1.1 AI and Machine Learning Workload Growth
5.1.2 Hyperscale Data Centre Expansion
5.1.3 Edge Computing and Distributed AI
5.2 Technology Trends
5.2.1 Technology Trends Overview
5.2.2 Technology Trends: Packaging
5.2.3 Universal Chiplet Interconnect Express (UCIe)
5.2.4 Laser Sources for CPO

6 MARKET OUTLOOK
6.1 Scale-Out Outlook
6.1.1 Scale-Out CPO Market Evolution
6.1.2 Scale-Out Technology Roadmap
6.1.3 Scale-Out Key Players and Competitive Landscape
6.2 Scale-Up Outlook
6.2.1 Scale-Up CPO Market Evolution
6.2.2 Scale-Up Technology Roadmap
6.2.3 Scale-Up Key Players and Competitive Landscape
6.3 High-Density Connectors

7 COMPANY PROFILES (55 COMPANY PROFILES)
8 APPENDIX
8.1 Research Methodology and Data Sources

9 REFERENCES
LIST OF TABLES
Table 1. CPO Market Drivers and Restraints Analysis
Table 2. Key Data Centre Architecture Challenges Summar
Table 3. CPO vs. Pluggables Decision Matrix
Table 4. Semiconductor Packaging Interconnection Techniques Overview
Table 5. CPO Application Segmentation (Scale-Out vs. Scale-Up)
Table 6. EIC/PIC Integration Methods Comparison
Table 7. Packaging Technology Benchmark for EIC/PIC Integration
Table 8. CPO Technology Challenges and Mitigation Strategies
Table 9. NVIDIA vs. Broadcom Strategic Positioning Comparison
Table 10. NVIDIA vs. Broadcom CPO Product Specifications Benchmark
Table 11. Server Boards, CPUs, and GPU/Accelerator Forecast (2026-2036)
Table 12. Optical I/O CPO Unit Shipment Forecast (2026-2036)
Table 13. Optical I/O CPO Revenue Forecast (2026-2036)
Table 14. CPO Network Switch Unit Shipment Forecast
Table 15. CPO Network Switch Revenue Forecast (2026-2036)
Table 16. Total CPO Market Size and Revenue (2026-2036)
Table 17. CPO Unit Shipments by Integration Technology
Table 18. Network Switch CPO Adoption by Packaging Technology
Table 19. Optical I/O Forecast by Packaging Technology
Table 20. PIC Design Segment - Key Players and Capabilities
Table 21. ASIC and xPU Design Segment - Key Players and CPO Integration Strategies
Table 22. Laser Sources Segment - Key Suppliers and Technologies
Table 23. SOI Wafer and Epi-Wafer Segment - Substrate Suppliers
Table 24. EIC, Retimers, SerDes, and PHY Segment - High-Speed Electronics Suppliers
Table 25. Connectors and Fibers Segment - Optical Infrastructure Suppliers
Table 26. Foundries Segment - Silicon Photonics and Advanced Packaging Capabilities
Table 27. Packaging, Assembling, and Testing Segment - OSAT and Test Equipment Providers
Table 28. System and Equipment Segment - OEMs and ODMs
Table 29. End Customers (Hyperscalers) Segment - Data Centre Operators and AI Leaders
Table 30. CPO Industrial Ecosystem Summary - Complete Value Chain Overview
Table 31. AI Data Centre Requirements by Workload Type
Table 32. Switch Hierarchy in AI Data Centres
Table 33. Scale-Up vs. Scale-Out vs. Scale-Across Comparison Matrix
Table 34. SerDes Bandwidth Limitations and Power Consumption
Table 35. SerDes Bottleneck Solutions Comparison
Table 36. Pluggable Optics Architecture and Limitations
Table 37. Signal Loss Comparison: Pluggable vs. CPO (dB)
Table 38. Comprehensive Pluggable vs. CPO Comparison
Table 39. Design Decision Framework for CPO Adoption
Table 40.Copper Wire Count in Current AI Systems
Table 41. Copper Interconnect Specifications by System
Table 42. Copper System Limitations Summary
Table 43. Copper vs. Optical Performance Benchmark
Table 44. Power Consumption by Interconnect Technology
Table 45. Latency Benchmark Comparison
Table 46. PICs vs. Silicon Photonics Comparison
Table 47. PIC Advantages and Challenges Summary
Table 48. CPO Technology Building Blocks
Table 49. CPO Technology Components and Suppliers
Table 50. Latency Comparison: Pluggable vs. CPO
Table 51. CPO Value Proposition Summary
Table 52. CPO Technical Challenges and Industry Solutions
Table 53. Advanced Optical I/O Integration Approaches
Table 54. CPO Packaging Technologies Overview
Table 55. Advanced Packaging Performance Metrics
Table 56. Silicon-Based 2.5D Packaging Options
Table 57. TSV Specifications and Trends
Table 58. Si Interposer vs. Si Bridge Comparison
Table 59. SiO2 vs. Organic Dielectric Comparison
Table 60. WLFO vs. PLFO Comparison
Table 61. Fan-Out Packaging Trends
Table 62. Fan-Out Process Challenges
Table 63. Glass Applications in Semiconductor Packaging
Table 64. Glass vs. Silicon Interposer Comparison
Table 65. Glass vs. Molding Compound Properties
Table 66. Glass Packaging Challenges and Solutions
Table 67. Bump Scaling Challenges
Table 68. Micro-Bump Specifications and Applications
Table 69. Cu-Cu Hybrid Bonding Methods Comparison
Table 70. Hybrid Bonding Manufacturing Challenges
Table 71. Conventional EIC/PIC Integration Methods
Table 72. Emerging EIC/PIC Integration Methods
Table 73. EIC/PIC Packaging Technology Benchmark
Table 74. 2D EIC/PIC Integration Pros and Cons
Table 75. 2.5D EIC/PIC Integration Pros and Cons
Table 76. 3D Hybrid EIC/PIC Integration Pros and Cons
Table 77. 3D Monolithic EIC/PIC Integration Pros and Cons
Table 78. Benefits of TSV for PIC/EIC Integration
Table 79. TSV Fabrication Challenges in CPO
Table 80. Si Photonics Packaging Options Comparison
Table 81. 2.5D Si Interposer Pros and Cons for EIC/PIC
Table 82. FOPOP vs. WB Packaging Comparison
Table 83. Optical Engine Packaging Process Challenges
Table 84. Fan-Out EIC/PIC Integration Challenges
Table 85. Co-Packaging vs. CPO Definition Comparison
Table 86. Future 3D-CPO Architecture Vision
Table 87. CPO Technology Challenges and Future Opportunities
Table 88. CPO Assembly Process and Bottlenecks
Table 89. Grating vs. Edge Coupler Comparison
Table 90. Optical Alignment Challenges Overview
Table 91. Active vs. Passive Alignment Comparison
Table 92. FAU Supplier Landscape
Table 93. On-Chip Laser Integration Approaches
Table 94. Laser Attach Technology Comparison
Table 95. Comprehensive Laser Integration Benchmark
Table 96. Global Hyperscale Data Centre Capacity
Table 97. Edge Computing Market Growth
Table 98. DATACOM Technology Trends Summary
Table 99. Packaging Technology Evolution for DATACOM
Table 100. UCIe Specifications and Adoption Timeline
Table 101. Laser Source Technology Trends
Table 102. Laser Source Comparison for CPO
Table 103. Scale-Up CPO Market Forecast

LIST OF FIGURES
Figure 1. Anatomy of a Modern AI Data Centre
Figure 2. Network Switch Architecture in Data Centres
Figure 3. Switch IC Bandwidth Evolution Timeline (2015-2036)
Figure 4. Optical Transceiver Technology Migration Path (Pluggable ? Near-Package ? CPO)
Figure 5. Optical Engine Component Architecture
Figure 6. Co-Packaged Optics 1.0: Typical Integration Flow
Figure 7. Heterogeneous Integration Concept Diagram
Figure 8. Evolution from 2D to 2.5D to 3D Integration
Figure 9. 3D Optical Engine Packaging Configuration Examples
Figure 10. Current State AI System Architecture
Figure 11. Server Boards, CPUs, and GPU/Accelerator Forecast (2026-2036)
Figure 12. Optical I/O CPO Unit Shipment Forecast (2026-2036)
Figure 13. Optical I/O CPO Revenue Forecast (2026-2036)
Figure 14. CPO Network Switch Unit Shipment Forecast
Figure 15. CPO Network Switch Revenue Forecast (2026-2036)
Figure 16. Total CPO Market Size and Revenue (2026-2036)
Figure 17. CPO Unit Shipments by Integration Technology
Figure 18. Network Switch CPO Adoption by Packaging Technology
Figure 19. Optical I/O Forecast by Packaging Technology
Figure 20. LLM Parameter Growth Timeline (GPT-1 to GPT-5 and Beyond)
Figure 21. Global AI Training Compute Demand Growth
Figure 22. NVIDIA DGX and HGX System Architecture
Figure 23. NVIDIA Rubin Architecture Overview
Figure 24. Three-Tier Network Architecture Diagram
Figure 25. Interconnect Technology Roadmap (2020-2036)
Figure 26. On-Board Optics Configuration
Figure 27. CPO Architecture and Signal Path
Figure 28. Switch ASIC Bandwidth Scaling (51.2T ? 102.4T ? 204.8T)
Figure 29. L2 Network Architecture Comparison
Figure 30. Copper-to-Optical Migration Roadmap
Figure 31. Current AI System Interconnect Architecture
Figure 32. L1 Backside Copper Architecture Diagram
Figure 33. L1 Backside CPO Architecture Diagram
Figure 34. Power Efficiency Comparison (pJ/bit)
Figure 35. AI Architecture Evolution (2026-2030)
Figure 36. AI Architecture Vision (2031-2036)
Figure 37. PIC Component Overview
Figure 38. PIC Architecture Diagram with Key Components
Figure 39. Optical Engine Block Diagram
Figure 40. Optical Engine Signal Flow (Electrical-to-Optical Conversion)
Figure 41. Optical Power Supply Configurations
Figure 42. CPO Key Concepts Illustration
Figure 43. Power Consumption Comparison (pJ/bit Roadmap)
Figure 44. Data Rate Scaling with CPO
Figure 45. Optical Transceiver Component Breakdown
Figure 46. Heterogeneous Integration Concept for CPO
Figure 47. CPO Network Switch Packaging Architecture
Figure 48. 1.6 Tbps CPO Module Configuration
Figure 49. Optical I/O Packaging for XPUs
Figure 50. Semiconductor Packaging Evolution Timeline
Figure 51. Semiconductor Packaging Technology Landscape
Figure 52. Interconnection Techniques Hierarchy
Figure 53. 2.5D Packaging Structure Diagram
Figure 54. TSV Technology Evolution
Figure 55. 2.5D Si-Based Packaging Roadmap
Figure 56. High-Density Fan-Out Packaging Architecture
Figure 57. RDL Structure and Manufacturing Process
Figure 58. Panel-Level Fan-Out Process
Figure 59. Wafer-Level Fan-Out Process
Figure 60. Glass Core Interposer Structure
Figure 61. Glass Interposer Manufacturing Process Flow
Figure 62. Bumping Technology Evolution Timeline
Figure 63. Cu-Cu Hybrid Bonding Process
Figure 64. EIC/PIC Integration Evolution (2D ? 2.5D ? 3D)
Figure 65. TSV-Based EIC/PIC Integration Architecture
Figure 66. Cisco Optical Engine Evolution
Figure 67. Cisco 2.5D CoC Architecture
Figure 68. Cisco 3D TSV Integration
Figure 69. TSV Fabrication Process Flow
Figure 70. ASE Fan-Out CPO Solution
Figure 71. ASE FOPOP Process Flow
Figure 72. SPIL's Fan-Out Embedded Bridge (FOEB) Structure for PIC/EIC Integration in CPO
Figure 73. FOEB Integration Process Flow
Figure 74. Rockley FOWLP CPO Structure
Figure 75. Corning Glass CPO Vision
Figure 76. Glass-Based CPO Package Structure
Figure 77. Glass CPO Process Development Roadmap
Figure 78. TSMC Optical Engine Roadmap
Figure 79. TSMC iOIS Architecture
Figure 80. SoIC Bond for EIC/PIC
Figure 81. Bond Pitch Scaling Roadmap
Figure 82. CPO ASIC Packaging Structure Types
Figure 83. 2D/2.5D OE IC Packaging Examples
Figure 84. 2.5D OE-ASIC Integration
Figure 85. 3D OE IC Packaging Examples
Figure 86. NVIDIA 3D Integration Architecture (TSV Interposer)
Figure 87. FAU Component Breakdown
Figure 88. AI Workload Growth Projections
Figure 89. Scale-Up Technology Evolution Timeline
Figure 90. Broadcom XPU-CPO Architecture
Figure 91. Broadcom's CPO Roadmap
Figure 92. Lightmatter M1000
Figure 93. Marvell XPU-CPO Architecture

Companies Mentioned (Partial List)

A selection of companies mentioned in this report includes, but is not limited to:

  • Alphawave Semi
  • AMD
  • Amkor Technology
  • ASE Holdings
  • Astera Labs
  • Avicena
  • AXT
  • Ayar Labs
  • Broadcom
  • CEA-Leti
  • Celestial AI
  • Cisco
  • Coherent
  • Corning
  • Credo
  • DenseLight
  • EFFECT Photonics
  • EVG
  • Fabrinet
  • FOCI (Fiber Optical Communication Inc.)
  • FormFactor
  • Foxconn
  • GlobalFoundries
  • Henkel
  • Hewlett Packard Enterprise
  • imec
  • Intel
  • JCET Group
  • Lightmatter
  • LioniX International
  • Lumentum
  • MACOM
  • Marvell
  • MediaTek
  • Molex
  • Nubis Communications
  • NVIDIA
  • OpenLight
  • Ranovus
  • Rockley Photonics
  • Samtec
  • Scintil Photonics