The global neural processing units (NPU) market was valued at USD 17.20 billion in 2025. It is estimated at USD 21.30 billion in 2026 and is forecast to reach USD 101.50 billion by 2036, growing at a CAGR of 16.9% over the 2026-2036 period. This report examines the market in depth, covering NPU adoption in AI PCs and smartphones, China's domestic data center NPUs, performance benchmarking, microarchitectures, memory and precision support, the software ecosystem, export controls, pricing, the value chain, competition, and future growth opportunities.
The study defines NPUs as processors and processor blocks built to speed up neural network workloads through large multiply-accumulate arrays, dedicated on-chip memory, and low-precision arithmetic. It covers NPUs integrated into the SoCs of phones, PCs, tablets, wearables, XR headsets, vehicles, cameras, and microcontrollers; discrete edge NPUs sold as chips or modules; data center NPUs, including Huawei Ascend and Cambricon MLU parts and the Korean chips of Rebellions and FuriosaAI; and NPU IP licensed by Arm, Cadence, Synopsys, CEVA, and VeriSilicon. Integrated NPUs are valued on the NPU-attributable portion of the chip, and IP on licensing and royalty income. GPUs and custom hyperscaler ASICs such as TPUs are excluded.
Dedicated AI engines are now a standard part of consumer computing, as Apple added its Neural Engine to iPhone processors in 2017, Intel brought NPUs to its Core Ultra PC processors at the end of 2023, and Microsoft's Copilot+ PC specification of 2024 sets a minimum NPU performance of 40 trillion operations per second (TOPS). In China, where U.S. export controls limit access to advanced GPUs, Cambricon reported its first annual profit in 2025 on revenue that rose 453% to RMB 6.497 billion, and Huawei announced Atlas SuperPoD systems linking 8,192 and 15,488 Ascend NPUs for late 2026 and late 2027.
Software fragmentation keeps many NPUs underused, since each architecture needs its own compiler, runtime, and quantization flow, and developers often fall back on GPUs or CPUs; Chinese vendors must also build alternatives to NVIDIA's CUDA. Generative AI models are often limited by memory bandwidth rather than compute, and Samsung reportedly raised some memory chip prices by as much as 60% in late 2025. Chinese NPUs face restricted access to high-bandwidth memory and leading-edge foundry nodes, which lowers per-chip performance and yields. Other challenges include fast-changing model architectures, the gap between headline TOPS and real application performance, competition from GPUs and CPU matrix extensions, power and die-area limits in mid-range devices, and the cost of scaling for independent developers, reflected in the 2024 Rebellions-Sapeon merger and NXP's 2025 agreement to acquire Kinara.
NPU IP licensing is a major opportunity, as microcontroller, IoT, and automotive chipmakers license proven cores such as Arm's Ethos-U85 rather than design their own, and NPUs reach low-cost parts such as STMicroelectronics' STM32N6. Sovereign programs in China and South Korea create protected demand, illustrated by FuriosaAI winning LG as a customer for its RNGD chip in 2025. Robotics adds further room for growth: the International Federation of Robotics counted 542,000 new industrial robots installed worldwide during 2024. Key trends include the NPU performance race in PCs, heterogeneous scheduling through Windows ML, Core ML, LiteRT, and ONNX Runtime, rack-scale NPU supernodes, and 8-bit and 4-bit low-precision inference.
By type, the report covers integrated NPUs, discrete edge NPUs, and data center NPUs. Integrated NPUs are expected to hold the largest share in 2026, as an NPU block is now built into the processors of billions of phones, PCs, and other devices, and each new platform raises NPU performance and the value attributed to it. Data center NPUs are expected to grow at the highest CAGR during the forecast period, driven by China's move to domestic AI accelerators under U.S. export controls, Cambricon's rapid revenue growth, and Huawei's SuperPoD systems linking thousands of Ascend NPUs. Discrete edge NPUs from Hailo, Axelera AI, and others serve cameras, gateways, and industrial systems that need extra AI performance next to the main processor.
By offering, the study splits the market into NPU silicon and NPU IP & licensing. NPU silicon is expected to account for the larger share in 2026, since it combines the NPU value inside device SoCs with the full value of discrete edge and data center chips, where Huawei and Cambricon are adding volume. NPU IP & licensing is expected to register the higher CAGR, as microcontroller, IoT, and automotive chipmakers add licensed cores such as Arm's Ethos-U85 instead of funding in-house design. Because royalties rise with unit shipments, the spread of NPUs into low-cost devices directly benefits Arm, Cadence, Synopsys, CEVA, and VeriSilicon.
The application analysis spans smartphones, PCs & tablets, wearables & XR, automotive, smart cameras & IoT, industrial & robotics, and data center & cloud AI. Smartphones are expected to hold the largest share in 2026, as more than a billion handsets are sold each year and each flagship platform adds NPU performance and memory bandwidth to run larger generative AI models locally. PCs & tablets are expected to grow at the highest CAGR, supported by the Copilot+ requirement, the refresh that followed the end of Windows 10 support, and rising NPU ratings from Qualcomm, Intel, AMD, and Apple. Automotive, smart cameras & IoT, and industrial & robotics add diversified demand, while data center & cloud AI tracks China's domestic NPU build-out.
By performance class, NPUs are grouped into below 10 TOPS, 10-100 TOPS, and above 100 TOPS. The 10-100 TOPS class is expected to hold the largest share in 2026, as it includes most phone NPUs, such as the roughly 35 TOPS Neural Engine in Apple's A17 Pro and A18 Pro, and the 45 to 50 TOPS PC NPUs built to meet the Copilot+ threshold. The above 100 TOPS class is expected to grow at the highest CAGR, driven by data center NPUs and by automotive processors that need far more compute for automated driving. The below 10 TOPS class serves microcontrollers, wearables, and IoT devices with very tight power budgets.
The architecture analysis covers fixed-function MAC arrays, programmable vector/SIMD, dataflow, and in-memory compute designs. The report does not name a leading or fastest-growing architecture; it examines the balance between efficiency and flexibility. Fixed-function arrays are highly efficient on established operators, but chips take two to three years to design and stay in use for years, so programmable designs gain importance as transformers and mixture-of-experts models bring new operators. Dataflow designs suit data center and edge accelerators, while in-memory compute addresses the memory bandwidth bottleneck.
Asia-Pacific is expected to remain the largest regional market in 2026, as the region leads in phone and PC manufacturing and NPU design, and China's domestic data center NPUs, led by Cambricon and Huawei's Atlas SuperPoD roadmap, add a large new demand base. Taiwan's MediaTek supplies NPU-equipped phone processors, South Korea hosts Samsung, Rebellions, and FuriosaAI, Japan contributes NPU work from Renesas and Sony, while LG's 2025 adoption of FuriosaAI's RNGD shows Korean NPUs winning domestic customers.
North America is expected to grow at the highest CAGR during the forecast period, supported by the AI PC upgrade cycle and the region's lead in NPU design, with Apple, Qualcomm, Intel, AMD, and Google building NPUs for phones and PCs and Cadence and Synopsys licensing NPU cores worldwide. Europe holds a significant share through Arm's NPU IP, the microcontroller and automotive NPUs of STMicroelectronics and NXP, and Axelera AI, and the EU Chips Act of 2023 targets more than EUR 43 billion in public and private semiconductor investment. Brazil and Mexico lead Latin America, where on-device AI is reaching mid-range phones, and Israel, home to Hailo and Mobileye, anchors edge AI design in the Middle East & Africa alongside Gulf AI and smart city investment.
The market brings together phone and PC chip designers that build their own NPUs, China's data center NPU makers, Korean startups, edge AI specialists, microcontroller and automotive chipmakers, and IP licensors. Vendors compete on performance per watt, real application performance rather than peak TOPS, software tools, memory efficiency, precision support, cost, and ecosystem partnerships. Main strategies include higher NPU ratings in each product generation, better compilers and scheduling, rack-scale NPU clusters, and wider IP licensing. Notable developments include Qualcomm's Snapdragon X2 Elite in 2025, Huawei's CloudMatrix 384 system in April 2025 followed by the Atlas 950 and 960 announcements, and Apple's M5 chip of October 2025 with neural accelerators in each GPU core.
Key companies profiled in the report include Apple Inc. (U.S.), Qualcomm Incorporated (U.S.), MediaTek Inc. (Taiwan), Samsung Electronics Co., Ltd. (South Korea), Google LLC (U.S.), Intel Corporation (U.S.), Advanced Micro Devices, Inc. (U.S.), Huawei Technologies Co., Ltd. (China), Cambricon Technologies Corporation Limited (China), Rebellions Inc. (South Korea), FuriosaAI, Inc. (South Korea), Hailo Technologies Ltd. (Israel), Axelera AI (Netherlands), Ambarella, Inc. (U.S.), Horizon Robotics (China), NXP Semiconductors N.V. (Netherlands), STMicroelectronics N.V. (Switzerland), Arm Holdings plc (U.K.), Cadence Design Systems, Inc. (U.S.), Synopsys, Inc. (U.S.), CEVA, Inc. (U.S.), and VeriSilicon Microelectronics (Shanghai) Co., Ltd. (China).
The study defines NPUs as processors and processor blocks built to speed up neural network workloads through large multiply-accumulate arrays, dedicated on-chip memory, and low-precision arithmetic. It covers NPUs integrated into the SoCs of phones, PCs, tablets, wearables, XR headsets, vehicles, cameras, and microcontrollers; discrete edge NPUs sold as chips or modules; data center NPUs, including Huawei Ascend and Cambricon MLU parts and the Korean chips of Rebellions and FuriosaAI; and NPU IP licensed by Arm, Cadence, Synopsys, CEVA, and VeriSilicon. Integrated NPUs are valued on the NPU-attributable portion of the chip, and IP on licensing and royalty income. GPUs and custom hyperscaler ASICs such as TPUs are excluded.
Dedicated AI engines are now a standard part of consumer computing, as Apple added its Neural Engine to iPhone processors in 2017, Intel brought NPUs to its Core Ultra PC processors at the end of 2023, and Microsoft's Copilot+ PC specification of 2024 sets a minimum NPU performance of 40 trillion operations per second (TOPS). In China, where U.S. export controls limit access to advanced GPUs, Cambricon reported its first annual profit in 2025 on revenue that rose 453% to RMB 6.497 billion, and Huawei announced Atlas SuperPoD systems linking 8,192 and 15,488 Ascend NPUs for late 2026 and late 2027.
Market Dynamics
The AI PC replacement cycle is a leading source of growth, as PC chipmakers lifted NPU ratings quickly after Microsoft set the 40 TOPS threshold, and 2024 processors from Qualcomm (Snapdragon X Elite), Intel (Lunar Lake), and AMD (Ryzen AI 300) were rated between 45 and 50 TOPS, while the retirement of Windows 10 in October 2025 is pushing users toward new NPU-equipped machines. Phone NPUs have moved from camera and voice tasks to on-device generative AI such as summarization, translation, and image editing, and Qualcomm reported fiscal 2025 handset revenue of USD 27.8 billion. U.S. chip restrictions, including the 2025 license requirement for NVIDIA's H20, are steering Chinese buyers to domestic NPUs, while vehicles, cameras, robots, and industrial devices add new demand; Qualcomm reported automotive revenue up 36% to a record USD 3.96 billion in fiscal 2025.Software fragmentation keeps many NPUs underused, since each architecture needs its own compiler, runtime, and quantization flow, and developers often fall back on GPUs or CPUs; Chinese vendors must also build alternatives to NVIDIA's CUDA. Generative AI models are often limited by memory bandwidth rather than compute, and Samsung reportedly raised some memory chip prices by as much as 60% in late 2025. Chinese NPUs face restricted access to high-bandwidth memory and leading-edge foundry nodes, which lowers per-chip performance and yields. Other challenges include fast-changing model architectures, the gap between headline TOPS and real application performance, competition from GPUs and CPU matrix extensions, power and die-area limits in mid-range devices, and the cost of scaling for independent developers, reflected in the 2024 Rebellions-Sapeon merger and NXP's 2025 agreement to acquire Kinara.
NPU IP licensing is a major opportunity, as microcontroller, IoT, and automotive chipmakers license proven cores such as Arm's Ethos-U85 rather than design their own, and NPUs reach low-cost parts such as STMicroelectronics' STM32N6. Sovereign programs in China and South Korea create protected demand, illustrated by FuriosaAI winning LG as a customer for its RNGD chip in 2025. Robotics adds further room for growth: the International Federation of Robotics counted 542,000 new industrial robots installed worldwide during 2024. Key trends include the NPU performance race in PCs, heterogeneous scheduling through Windows ML, Core ML, LiteRT, and ONNX Runtime, rack-scale NPU supernodes, and 8-bit and 4-bit low-precision inference.
Segment Analysis
The report analyzes the market by type, offering, application, performance class, architecture, and geography, helping stakeholders identify where NPU value is concentrated today and where it is shifting.By type, the report covers integrated NPUs, discrete edge NPUs, and data center NPUs. Integrated NPUs are expected to hold the largest share in 2026, as an NPU block is now built into the processors of billions of phones, PCs, and other devices, and each new platform raises NPU performance and the value attributed to it. Data center NPUs are expected to grow at the highest CAGR during the forecast period, driven by China's move to domestic AI accelerators under U.S. export controls, Cambricon's rapid revenue growth, and Huawei's SuperPoD systems linking thousands of Ascend NPUs. Discrete edge NPUs from Hailo, Axelera AI, and others serve cameras, gateways, and industrial systems that need extra AI performance next to the main processor.
By offering, the study splits the market into NPU silicon and NPU IP & licensing. NPU silicon is expected to account for the larger share in 2026, since it combines the NPU value inside device SoCs with the full value of discrete edge and data center chips, where Huawei and Cambricon are adding volume. NPU IP & licensing is expected to register the higher CAGR, as microcontroller, IoT, and automotive chipmakers add licensed cores such as Arm's Ethos-U85 instead of funding in-house design. Because royalties rise with unit shipments, the spread of NPUs into low-cost devices directly benefits Arm, Cadence, Synopsys, CEVA, and VeriSilicon.
The application analysis spans smartphones, PCs & tablets, wearables & XR, automotive, smart cameras & IoT, industrial & robotics, and data center & cloud AI. Smartphones are expected to hold the largest share in 2026, as more than a billion handsets are sold each year and each flagship platform adds NPU performance and memory bandwidth to run larger generative AI models locally. PCs & tablets are expected to grow at the highest CAGR, supported by the Copilot+ requirement, the refresh that followed the end of Windows 10 support, and rising NPU ratings from Qualcomm, Intel, AMD, and Apple. Automotive, smart cameras & IoT, and industrial & robotics add diversified demand, while data center & cloud AI tracks China's domestic NPU build-out.
By performance class, NPUs are grouped into below 10 TOPS, 10-100 TOPS, and above 100 TOPS. The 10-100 TOPS class is expected to hold the largest share in 2026, as it includes most phone NPUs, such as the roughly 35 TOPS Neural Engine in Apple's A17 Pro and A18 Pro, and the 45 to 50 TOPS PC NPUs built to meet the Copilot+ threshold. The above 100 TOPS class is expected to grow at the highest CAGR, driven by data center NPUs and by automotive processors that need far more compute for automated driving. The below 10 TOPS class serves microcontrollers, wearables, and IoT devices with very tight power budgets.
The architecture analysis covers fixed-function MAC arrays, programmable vector/SIMD, dataflow, and in-memory compute designs. The report does not name a leading or fastest-growing architecture; it examines the balance between efficiency and flexibility. Fixed-function arrays are highly efficient on established operators, but chips take two to three years to design and stay in use for years, so programmable designs gain importance as transformers and mixture-of-experts models bring new operators. Dataflow designs suit data center and edge accelerators, while in-memory compute addresses the memory bandwidth bottleneck.
Regional Analysis
Geographic coverage includes North America, Europe, Asia-Pacific, Latin America, and the Middle East & Africa, with analysis of 17 countries, the Nordic countries, and five rest-of-region groups. The regional analysis considers device and vehicle manufacturing, NPU design capability, data center investment, export control exposure, and AI PC and on-device AI adoption.Asia-Pacific is expected to remain the largest regional market in 2026, as the region leads in phone and PC manufacturing and NPU design, and China's domestic data center NPUs, led by Cambricon and Huawei's Atlas SuperPoD roadmap, add a large new demand base. Taiwan's MediaTek supplies NPU-equipped phone processors, South Korea hosts Samsung, Rebellions, and FuriosaAI, Japan contributes NPU work from Renesas and Sony, while LG's 2025 adoption of FuriosaAI's RNGD shows Korean NPUs winning domestic customers.
North America is expected to grow at the highest CAGR during the forecast period, supported by the AI PC upgrade cycle and the region's lead in NPU design, with Apple, Qualcomm, Intel, AMD, and Google building NPUs for phones and PCs and Cadence and Synopsys licensing NPU cores worldwide. Europe holds a significant share through Arm's NPU IP, the microcontroller and automotive NPUs of STMicroelectronics and NXP, and Axelera AI, and the EU Chips Act of 2023 targets more than EUR 43 billion in public and private semiconductor investment. Brazil and Mexico lead Latin America, where on-device AI is reaching mid-range phones, and Israel, home to Hailo and Mobileye, anchors edge AI design in the Middle East & Africa alongside Gulf AI and smart city investment.
Competitive Landscape
The report reviews key growth strategies, competitive benchmarking, and the competitive dashboard, which places companies among industry leaders, market differentiators, vanguards, and emerging companies, together with a 2025 market share/rank analysis. Profiles are grouped into device SoC leaders, data center NPU developers, edge NPU specialists, microcontroller and automotive chipmakers, and NPU IP providers, and cover business overview, financial overview, product portfolio, strategic developments, and SWOT analysis.The market brings together phone and PC chip designers that build their own NPUs, China's data center NPU makers, Korean startups, edge AI specialists, microcontroller and automotive chipmakers, and IP licensors. Vendors compete on performance per watt, real application performance rather than peak TOPS, software tools, memory efficiency, precision support, cost, and ecosystem partnerships. Main strategies include higher NPU ratings in each product generation, better compilers and scheduling, rack-scale NPU clusters, and wider IP licensing. Notable developments include Qualcomm's Snapdragon X2 Elite in 2025, Huawei's CloudMatrix 384 system in April 2025 followed by the Atlas 950 and 960 announcements, and Apple's M5 chip of October 2025 with neural accelerators in each GPU core.
Key companies profiled in the report include Apple Inc. (U.S.), Qualcomm Incorporated (U.S.), MediaTek Inc. (Taiwan), Samsung Electronics Co., Ltd. (South Korea), Google LLC (U.S.), Intel Corporation (U.S.), Advanced Micro Devices, Inc. (U.S.), Huawei Technologies Co., Ltd. (China), Cambricon Technologies Corporation Limited (China), Rebellions Inc. (South Korea), FuriosaAI, Inc. (South Korea), Hailo Technologies Ltd. (Israel), Axelera AI (Netherlands), Ambarella, Inc. (U.S.), Horizon Robotics (China), NXP Semiconductors N.V. (Netherlands), STMicroelectronics N.V. (Switzerland), Arm Holdings plc (U.K.), Cadence Design Systems, Inc. (U.S.), Synopsys, Inc. (U.S.), CEVA, Inc. (U.S.), and VeriSilicon Microelectronics (Shanghai) Co., Ltd. (China).
How This Report Helps
- Provides reliable market size estimates and long-term forecasts for the global neural processing units (NPU) market through 2036.
- Explains how AI PC requirements, on-device generative AI in smartphones, and China's domestic AI chip push are shaping NPU demand.
- Assesses the impact of software fragmentation, memory bandwidth and cost, export controls, and power and area budgets on NPU adoption.
- Identifies high-growth opportunities across type, offering, application, performance class, architecture, and region.
- Tracks technology developments such as rack-scale NPU supernodes, low-precision inference, heterogeneous scheduling, and configurable NPU IP cores.
- Benchmarks leading SoC designers, data center NPU developers, edge AI specialists, and IP providers on products, strategies, and market position.
- Supports product planning, IP licensing, partnership, investment, and market entry decisions for chipmakers, device and vehicle OEMs, cloud operators, and investors.
Key Questions Answered
- How large is the global NPU market today, and how will it grow through 2036?
- How are the Copilot+ PC requirement and the end of Windows 10 support changing NPU demand in PCs?
- What are the main drivers, restraints, opportunities, challenges, and trends shaping the market?
- How fast are domestic data center NPUs scaling in China, and how do export controls affect their performance?
- Which type, offering, application, and performance class segments will grow the fastest?
- How important will NPU IP licensing become as AI engines reach microcontrollers and IoT devices?
- Which regions and countries offer the most attractive opportunities for NPU suppliers?
- Who are the leading companies in the market, and how do they compare?
- What product launches, mergers, acquisitions, and system announcements are shaping competition?
Table of Contents
1. Introduction
2. Research Methodology
4. Market Overview
5. NPU Market, by Type
6. NPU Market, by Offering
7. NPU Market, by Application
8. NPU Market, by Performance Class
9. NPU Market, by Architecture
10. NPU Market, by Geography
11. Competitive Landscape
12. Company Profiles
13. Appendix
LIST OF TABLES
LIST OF FIGURES
Companies Mentioned
- Apple Inc.
- Qualcomm Incorporated
- MediaTek Inc.
- Samsung Electronics Co., Ltd.
- Google LLC
- Intel Corporation
- Advanced Micro Devices, Inc.
- Huawei Technologies Co., Ltd.
- Cambricon Technologies Corporation Limited
- Rebellions Inc.
- FuriosaAI, Inc.
- Hailo Technologies Ltd.
- Axelera AI
- Ambarella, Inc.
- Horizon Robotics
- NXP Semiconductors N.V.
- STMicroelectronics N.V.
- Arm Holdings plc
- Cadence Design Systems, Inc.
- Synopsys, Inc.
- CEVA, Inc.
- VeriSilicon Microelectronics
