Handbook of 3D Integration, Voume 4. Design, Test, and Thermal Management

  • ID: 4392525
  • Book
  • 472 Pages
  • John Wiley and Sons Ltd
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This fourth volume of the landmark handbook focuses on the design, testing and thermal management of 3D–integrated devices, both from a technological and a materials science perspective.

Edited and authored by key figures from top research institutions and high–tech companies, the first part of the book provides an overview of the latest developments in 3D chip design, including the particular challenges and potential. The second part is concerned with the test methods used to assess the quality and reliability of the 3D–integrated devices, while the third and final part deals with thermal management.

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PART I: DESIGN

3D Design Styles

Design Enablement and Advantages of Ultra–Fine Pitched 3D–Stacked Integrated Circuits

Wyoming Case Study

IBM Interposers

Interposer Interconnect Circuits

Signal Integrity for 3D

Power Integrity for 3D

2.5D/3D Design Flow

Monolithic 3D

EDA for 3D

3D Memories

3D Clock Distribution

PART II: TEST

Cost Modelling for 2.5D and 3D Stacked ICs

Interconnect Testing for 2.5D and 3D Stacked ICs

Pre–Bond Testing Through Direct Probing of Large–Array Fine–Pitch Micro–Bumps

3D Design–for–Test Architecture

Optimization of Test–Access Architectures and Test Scheduling for 3D ICs

IEEE P1838 3D Test Access Standard–in–Development

Test and Debug Strategy for TSMC CoWoS Stacking Process Based Heterogeneous 3D IC: A Silicon Case Study

PART III: THERMAL MANAGEMENT

Thermal Challenges and Emerging Solutions for 3D and 2.5D IC

Thermal Modeling and Experimental Model Validation for 3D Stacked ICs

Thermal Design for 3D ICs with Micro–Fluidics

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Philip Garrou
Mitsumasa Koyanagi
Peter Ramm
Paul D. Franzon
Eric J. Marinissen
Muhannad S. Bakir
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